blob: 4b0a791e79fa29eeabef0f4066899112f7291c57 [file] [log] [blame]
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +01001/*
2 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <lib/psci/psci.h>
8#include <plat/arm/common/plat_arm.h>
Emekcan Aras53e91a32021-11-17 18:45:32 +00009#include <platform_def.h>
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +010010/*******************************************************************************
11 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
12 * platform layer will take care of registering the handlers with PSCI.
13 ******************************************************************************/
Emekcan Aras53e91a32021-11-17 18:45:32 +000014
15static void __dead2 corstone1000_system_reset(void)
16{
17
18 uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
19 uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
20
21 *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
22 *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
23 while (1) {
David Vinczebfdb7262022-03-03 14:35:51 +010024 wfi();
25 }
Emekcan Aras53e91a32021-11-17 18:45:32 +000026}
27
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +010028plat_psci_ops_t plat_arm_psci_pm_ops = {
Emekcan Aras53e91a32021-11-17 18:45:32 +000029 .system_reset = corstone1000_system_reset,
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +010030 .validate_ns_entrypoint = NULL
31};
32
33const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
34{
Emekcan Aras53e91a32021-11-17 18:45:32 +000035 ops = &plat_arm_psci_pm_ops;
Abdellatif El Khlifiad9b8e52021-04-21 17:20:43 +010036 return ops;
37}