blob: fa5e4fa96593321426cf6d1ba29fcc63039a8786 [file] [log] [blame]
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01001/*
Carlo Caione1afdfb02019-08-24 18:47:06 +01002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz272e8712018-09-18 01:36:00 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef GXBB_DEF_H
8#define GXBB_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010011
12/*******************************************************************************
13 * System oscillator
14 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010015#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010016
17/*******************************************************************************
18 * Memory regions
19 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010020#define AML_NSDRAM0_BASE UL(0x01000000)
21#define AML_NSDRAM0_SIZE UL(0x0F000000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010022
Carlo Caione1e3e33b2019-08-28 15:32:22 +010023#define AML_NSDRAM1_BASE UL(0x10000000)
24#define AML_NSDRAM1_SIZE UL(0x00100000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010025
26#define BL31_BASE UL(0x10100000)
27#define BL31_SIZE UL(0x000C0000)
28#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
29
30/* Shared memory used for SMC services */
Carlo Caione107df3e2019-08-26 13:04:12 +010031#define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000)
32#define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010033
Carlo Caione1e3e33b2019-08-28 15:32:22 +010034#define AML_SEC_DEVICE0_BASE UL(0xC0000000)
35#define AML_SEC_DEVICE0_SIZE UL(0x09000000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010036
Carlo Caione1e3e33b2019-08-28 15:32:22 +010037#define AML_SEC_DEVICE1_BASE UL(0xD0040000)
38#define AML_SEC_DEVICE1_SIZE UL(0x00008000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010039
Carlo Caione1e3e33b2019-08-28 15:32:22 +010040#define AML_TZRAM_BASE UL(0xD9000000)
41#define AML_TZRAM_SIZE UL(0x00014000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010042/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
43
44/* Mailboxes */
Carlo Caione9c85f252019-08-28 09:46:18 +010045#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
46#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
Carlo Caione883e3ca2019-08-28 15:19:56 +010047#define AML_PSCI_MAILBOX_BASE UL(0xD9013F00)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010048
Carlo Caione1e3e33b2019-08-28 15:32:22 +010049#define AML_TZROM_BASE UL(0xD9040000)
50#define AML_TZROM_SIZE UL(0x00010000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010051
Carlo Caione1e3e33b2019-08-28 15:32:22 +010052#define AML_SEC_DEVICE2_BASE UL(0xDA000000)
53#define AML_SEC_DEVICE2_SIZE UL(0x00200000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010054
Carlo Caione1e3e33b2019-08-28 15:32:22 +010055#define AML_SEC_DEVICE3_BASE UL(0xDA800000)
56#define AML_SEC_DEVICE3_SIZE UL(0x00200000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010057
58/*******************************************************************************
59 * GIC-400 and interrupt handling related constants
60 ******************************************************************************/
Carlo Caione60c828b2019-08-24 18:51:48 +010061#define AML_GICD_BASE UL(0xC4301000)
62#define AML_GICC_BASE UL(0xC4302000)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010063
64#define IRQ_SEC_PHY_TIMER 29
65
66#define IRQ_SEC_SGI_0 8
67#define IRQ_SEC_SGI_1 9
68#define IRQ_SEC_SGI_2 10
69#define IRQ_SEC_SGI_3 11
70#define IRQ_SEC_SGI_4 12
71#define IRQ_SEC_SGI_5 13
72#define IRQ_SEC_SGI_6 14
73#define IRQ_SEC_SGI_7 15
74
75/*******************************************************************************
76 * UART definitions
77 ******************************************************************************/
Carlo Caione1afdfb02019-08-24 18:47:06 +010078#define AML_UART0_AO_BASE UL(0xC81004C0)
Carlo Caione1e3e33b2019-08-28 15:32:22 +010079#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
Carlo Caione1afdfb02019-08-24 18:47:06 +010080#define AML_UART_BAUDRATE U(115200)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010081
82/*******************************************************************************
83 * Memory-mapped I/O Registers
84 ******************************************************************************/
Carlo Caione1e3e33b2019-08-28 15:32:22 +010085#define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010086
Carlo Caione1e3e33b2019-08-28 15:32:22 +010087#define AML_SYS_CPU_CFG7 UL(0xC8834664)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010088
Carlo Caione883e3ca2019-08-28 15:19:56 +010089#define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010090
Carlo Caione9c85f252019-08-28 09:46:18 +010091#define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404)
92#define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
93#define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
94#define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428)
95#define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
96#define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +010097
Carlo Caionedc52a052019-09-18 10:12:35 +010098#define AML_SHA_DMA_BASE UL(0xC883E000)
99#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
100#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18)
101
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100102/*******************************************************************************
103 * System Monitor Call IDs and arguments
104 ******************************************************************************/
Carlo Caione107df3e2019-08-26 13:04:12 +0100105#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
106#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100107
Carlo Caione107df3e2019-08-26 13:04:12 +0100108#define AML_SM_EFUSE_READ U(0x82000030)
109#define AML_SM_EFUSE_USER_MAX U(0x82000033)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100110
Carlo Caione107df3e2019-08-26 13:04:12 +0100111#define AML_SM_JTAG_ON U(0x82000040)
112#define AML_SM_JTAG_OFF U(0x82000041)
Carlo Caionef7c4f9b2019-09-16 12:13:49 +0100113#define AML_SM_GET_CHIP_ID U(0x82000044)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100114
Carlo Caione107df3e2019-08-26 13:04:12 +0100115#define AML_JTAG_STATE_ON U(0)
116#define AML_JTAG_STATE_OFF U(1)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100117
Carlo Caione107df3e2019-08-26 13:04:12 +0100118#define AML_JTAG_M3_AO U(0)
119#define AML_JTAG_M3_EE U(1)
120#define AML_JTAG_A53_AO U(2)
121#define AML_JTAG_A53_EE U(3)
Antonio Nino Diaz272e8712018-09-18 01:36:00 +0100122
123#endif /* GXBB_DEF_H */