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Achin Gupta607084e2014-02-09 18:24:19 +00001/*
Soby Mathewda43b662015-07-08 21:45:46 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta607084e2014-02-09 18:24:19 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta607084e2014-02-09 18:24:19 +000031#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <assert.h>
33#include <bl_common.h>
Achin Gupta607084e2014-02-09 18:24:19 +000034#include <context_mgmt.h>
Achin Gupta607084e2014-02-09 18:24:19 +000035#include <debug.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010036#include <platform.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <tsp.h>
Dan Handley714a0d22014-04-09 13:13:04 +010038#include "tspd_private.h"
Achin Gupta607084e2014-02-09 18:24:19 +000039
40/*******************************************************************************
41 * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions
42 * needed. Nothing at the moment.
43 ******************************************************************************/
44static void tspd_cpu_on_handler(uint64_t target_cpu)
45{
46}
47
48/*******************************************************************************
49 * This cpu is being turned off. Allow the TSPD/TSP to perform any actions
50 * needed
51 ******************************************************************************/
Soby Mathewf5121572014-09-30 11:19:51 +010052static int32_t tspd_cpu_off_handler(uint64_t unused)
Achin Gupta607084e2014-02-09 18:24:19 +000053{
54 int32_t rc = 0;
Soby Mathewda43b662015-07-08 21:45:46 +010055 uint32_t linear_id = plat_my_core_pos();
Dan Handleye2712bc2014-04-10 15:37:22 +010056 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +000057
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010058 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +010059 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +000060
61 /* Program the entry point and enter the TSP */
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010062 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry);
Achin Gupta607084e2014-02-09 18:24:19 +000063 rc = tspd_synchronous_sp_entry(tsp_ctx);
64
65 /*
66 * Read the response from the TSP. A non-zero return means that
67 * something went wrong while communicating with the TSP.
68 */
69 if (rc != 0)
70 panic();
71
72 /*
73 * Reset TSP's context for a fresh start when this cpu is turned on
74 * subsequently.
75 */
Achin Gupta18d6eaf2014-05-04 18:23:26 +010076 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF);
Achin Gupta607084e2014-02-09 18:24:19 +000077
78 return 0;
79}
80
81/*******************************************************************************
82 * This cpu is being suspended. S-EL1 state must have been saved in the
83 * resident cpu (mpidr format) if it is a UP/UP migratable TSP.
84 ******************************************************************************/
Achin Gupta9a0ff9b2015-09-07 20:43:27 +010085static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl)
Achin Gupta607084e2014-02-09 18:24:19 +000086{
87 int32_t rc = 0;
Soby Mathewda43b662015-07-08 21:45:46 +010088 uint32_t linear_id = plat_my_core_pos();
Dan Handleye2712bc2014-04-10 15:37:22 +010089 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +000090
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010091 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +010092 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +000093
Soby Mathewf5121572014-09-30 11:19:51 +010094 /* Program the entry point and enter the TSP */
Andrew Thoelke891c4ca2014-05-20 21:43:27 +010095 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry);
Achin Gupta607084e2014-02-09 18:24:19 +000096 rc = tspd_synchronous_sp_entry(tsp_ctx);
97
98 /*
99 * Read the response from the TSP. A non-zero return means that
100 * something went wrong while communicating with the TSP.
101 */
102 if (rc != 0)
103 panic();
104
105 /* Update its context to reflect the state the TSP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100106 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND);
Achin Gupta607084e2014-02-09 18:24:19 +0000107}
108
109/*******************************************************************************
110 * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits
111 * before passing control back to the Secure Monitor. Entry in S-El1 is done
112 * after initialising minimal architectural state that guarantees safe
113 * execution.
114 ******************************************************************************/
Soby Mathewf5121572014-09-30 11:19:51 +0100115static void tspd_cpu_on_finish_handler(uint64_t unused)
Achin Gupta607084e2014-02-09 18:24:19 +0000116{
117 int32_t rc = 0;
Soby Mathewda43b662015-07-08 21:45:46 +0100118 uint32_t linear_id = plat_my_core_pos();
Dan Handleye2712bc2014-04-10 15:37:22 +0100119 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100120 entry_point_info_t tsp_on_entrypoint;
Achin Gupta607084e2014-02-09 18:24:19 +0000121
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100122 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100123 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF);
Achin Gupta607084e2014-02-09 18:24:19 +0000124
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100125 tspd_init_tsp_ep_state(&tsp_on_entrypoint,
Achin Gupta607084e2014-02-09 18:24:19 +0000126 TSP_AARCH64,
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100127 (uint64_t) &tsp_vectors->cpu_on_entry,
Achin Gupta607084e2014-02-09 18:24:19 +0000128 tsp_ctx);
129
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100130 /* Initialise this cpu's secure context */
Soby Mathewda43b662015-07-08 21:45:46 +0100131 cm_init_my_context(&tsp_on_entrypoint);
Vikram Kanigiri9d70f0f2014-07-15 16:46:43 +0100132
Soby Mathewbec98512015-09-03 18:29:38 +0100133#if TSP_NS_INTR_ASYNC_PREEMPT
Soby Mathew47903c02015-01-13 15:48:26 +0000134 /*
135 * Disable the NS interrupt locally since it will be enabled globally
Soby Mathewda43b662015-07-08 21:45:46 +0100136 * within cm_init_my_context.
Soby Mathew47903c02015-01-13 15:48:26 +0000137 */
138 disable_intr_rm_local(INTR_TYPE_NS, SECURE);
139#endif
140
Achin Gupta607084e2014-02-09 18:24:19 +0000141 /* Enter the TSP */
142 rc = tspd_synchronous_sp_entry(tsp_ctx);
143
144 /*
145 * Read the response from the TSP. A non-zero return means that
146 * something went wrong while communicating with the SP.
147 */
148 if (rc != 0)
149 panic();
150
151 /* Update its context to reflect the state the SP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100152 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +0000153}
154
155/*******************************************************************************
156 * This cpu has resumed from suspend. The SPD saved the TSP context when it
157 * completed the preceding suspend call. Use that context to program an entry
158 * into the TSP to allow it to do any remaining book keeping
159 ******************************************************************************/
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100160static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl)
Achin Gupta607084e2014-02-09 18:24:19 +0000161{
162 int32_t rc = 0;
Soby Mathewda43b662015-07-08 21:45:46 +0100163 uint32_t linear_id = plat_my_core_pos();
Dan Handleye2712bc2014-04-10 15:37:22 +0100164 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
Achin Gupta607084e2014-02-09 18:24:19 +0000165
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100166 assert(tsp_vectors);
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100167 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND);
Achin Gupta607084e2014-02-09 18:24:19 +0000168
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100169 /* Program the entry point, max_off_pwrlvl and enter the SP */
Achin Gupta607084e2014-02-09 18:24:19 +0000170 write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
171 CTX_GPREG_X0,
Achin Gupta9a0ff9b2015-09-07 20:43:27 +0100172 max_off_pwrlvl);
Andrew Thoelke891c4ca2014-05-20 21:43:27 +0100173 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
Achin Gupta607084e2014-02-09 18:24:19 +0000174 rc = tspd_synchronous_sp_entry(tsp_ctx);
175
176 /*
177 * Read the response from the TSP. A non-zero return means that
178 * something went wrong while communicating with the TSP.
179 */
180 if (rc != 0)
181 panic();
182
183 /* Update its context to reflect the state the SP is in */
Achin Gupta18d6eaf2014-05-04 18:23:26 +0100184 set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON);
Achin Gupta607084e2014-02-09 18:24:19 +0000185}
186
187/*******************************************************************************
188 * Return the type of TSP the TSPD is dealing with. Report the current resident
189 * cpu (mpidr format) if it is a UP/UP migratable TSP.
190 ******************************************************************************/
191static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu)
192{
193 return TSP_MIGRATE_INFO;
194}
195
196/*******************************************************************************
Juan Castillo4dc4a472014-08-12 11:17:06 +0100197 * System is about to be switched off. Allow the TSPD/TSP to perform
198 * any actions needed.
199 ******************************************************************************/
200static void tspd_system_off(void)
201{
Soby Mathewda43b662015-07-08 21:45:46 +0100202 uint32_t linear_id = plat_my_core_pos();
Juan Castillo4dc4a472014-08-12 11:17:06 +0100203 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
204
205 assert(tsp_vectors);
206 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
207
208 /* Program the entry point */
209 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry);
210
211 /* Enter the TSP. We do not care about the return value because we
212 * must continue the shutdown anyway */
213 tspd_synchronous_sp_entry(tsp_ctx);
214}
215
216/*******************************************************************************
217 * System is about to be reset. Allow the TSPD/TSP to perform
218 * any actions needed.
219 ******************************************************************************/
220static void tspd_system_reset(void)
221{
Soby Mathewda43b662015-07-08 21:45:46 +0100222 uint32_t linear_id = plat_my_core_pos();
Juan Castillo4dc4a472014-08-12 11:17:06 +0100223 tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id];
224
225 assert(tsp_vectors);
226 assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON);
227
228 /* Program the entry point */
229 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry);
230
231 /* Enter the TSP. We do not care about the return value because we
232 * must continue the reset anyway */
233 tspd_synchronous_sp_entry(tsp_ctx);
234}
235
236/*******************************************************************************
Achin Gupta607084e2014-02-09 18:24:19 +0000237 * Structure populated by the TSP Dispatcher to be given a chance to perform any
238 * TSP bookkeeping before PSCI executes a power mgmt. operation.
239 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100240const spd_pm_ops_t tspd_pm = {
Juan Castillo4dc4a472014-08-12 11:17:06 +0100241 .svc_on = tspd_cpu_on_handler,
242 .svc_off = tspd_cpu_off_handler,
243 .svc_suspend = tspd_cpu_suspend_handler,
244 .svc_on_finish = tspd_cpu_on_finish_handler,
245 .svc_suspend_finish = tspd_cpu_suspend_finish_handler,
246 .svc_migrate = NULL,
247 .svc_migrate_info = tspd_cpu_migrate_info,
248 .svc_system_off = tspd_system_off,
249 .svc_system_reset = tspd_system_reset
Achin Gupta607084e2014-02-09 18:24:19 +0000250};