blob: 03df421fc64ebb3c0478240f4ca813c02080c5ac [file] [log] [blame]
Caesar Wangf33eb2c2016-10-27 01:13:16 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wangf33eb2c2016-10-27 01:13:16 +08005 */
6
7#ifndef __SOC_ROCKCHIP_RK3399_SUSPEND_H__
8#define __SOC_ROCKCHIP_RK3399_SUSPEND_H__
9#include <dram.h>
10
11#define KHz (1000)
12#define MHz (1000 * KHz)
13#define GHz (1000 * MHz)
14
15#define PI_CA_TRAINING (1 << 0)
16#define PI_WRITE_LEVELING (1 << 1)
17#define PI_READ_GATE_TRAINING (1 << 2)
18#define PI_READ_LEVELING (1 << 3)
19#define PI_WDQ_LEVELING (1 << 4)
20#define PI_FULL_TRAINING (0xff)
21
22void dmc_save(void);
23__sramfunc void dmc_restore(void);
24__sramfunc void sram_regcpy(uintptr_t dst, uintptr_t src, uint32_t num);
25
26#endif /* __DRAM_H__ */