Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <platform_def.h> |
| 10 | #include <pmu_sram.h> |
| 11 | |
| 12 | .globl pmu_cpuson_entrypoint_start |
| 13 | .globl pmu_cpuson_entrypoint_end |
| 14 | |
| 15 | func pmu_cpuson_entrypoint |
| 16 | pmu_cpuson_entrypoint_start: |
| 17 | ldr x5, psram_data |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 18 | check_wake_cpus: |
| 19 | mrs x0, MPIDR_EL1 |
| 20 | and x1, x0, #MPIDR_CPU_MASK |
| 21 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 22 | orr x0, x0, x1 |
| 23 | /* primary_cpu */ |
| 24 | ldr w1, [x5, #PSRAM_DT_MPIDR] |
| 25 | cmp w0, w1 |
| 26 | b.eq sys_wakeup |
| 27 | /* |
| 28 | * If the core is not the primary cpu, |
| 29 | * force the core into wfe. |
| 30 | */ |
| 31 | wfe_loop: |
| 32 | wfe |
| 33 | b wfe_loop |
| 34 | sys_wakeup: |
| 35 | /* check ddr flag for resume ddr */ |
| 36 | ldr w2, [x5, #PSRAM_DT_DDRFLAG] |
| 37 | cmp w2, #0x0 |
| 38 | b.eq sys_resume |
| 39 | ddr_resume: |
| 40 | ldr x2, [x5, #PSRAM_DT_SP] |
| 41 | mov sp, x2 |
| 42 | ldr x1, [x5, #PSRAM_DT_DDR_FUNC] |
| 43 | ldr x0, [x5, #PSRAM_DT_DDR_DATA] |
| 44 | blr x1 |
| 45 | sys_resume: |
| 46 | ldr x1, sys_wakeup_entry |
| 47 | br x1 |
| 48 | |
| 49 | .align 3 |
| 50 | psram_data: |
| 51 | .quad PSRAM_DT_BASE |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 52 | sys_wakeup_entry: |
| 53 | .quad psci_entrypoint |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 54 | pmu_cpuson_entrypoint_end: |
| 55 | .word 0 |
| 56 | endfunc pmu_cpuson_entrypoint |