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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#include <arch_helpers.h>
8#include <arm_gic.h>
9#include <bl_common.h>
10#include <cci.h>
11#include <debug.h>
12#include <string.h>
13#include <xlat_tables.h>
14#include <platform_def.h>
15#include <plat_private.h>
Sandrine Bailleux7659a262016-07-05 09:55:03 +010016#include <utils.h>
Tony Xief6118cc2016-01-15 17:17:32 +080017
18#ifdef PLAT_RK_CCI_BASE
19static const int cci_map[] = {
20 PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX,
21 PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX
22};
23#endif
24
25/******************************************************************************
26 * Macro generating the code for the function setting up the pagetables as per
27 * the platform memory map & initialize the mmu, for the given exception level
28 ******************************************************************************/
29#define DEFINE_CONFIGURE_MMU_EL(_el) \
30 void plat_configure_mmu_el ## _el(unsigned long total_base, \
31 unsigned long total_size, \
32 unsigned long ro_start, \
33 unsigned long ro_limit, \
34 unsigned long coh_start, \
35 unsigned long coh_limit) \
36 { \
37 mmap_add_region(total_base, total_base, \
38 total_size, \
39 MT_MEMORY | MT_RW | MT_SECURE); \
40 mmap_add_region(ro_start, ro_start, \
41 ro_limit - ro_start, \
42 MT_MEMORY | MT_RO | MT_SECURE); \
43 mmap_add_region(coh_start, coh_start, \
44 coh_limit - coh_start, \
45 MT_DEVICE | MT_RW | MT_SECURE); \
46 mmap_add(plat_rk_mmap); \
Caesar Wangd90f43e2016-10-11 09:36:00 +080047 rockchip_plat_sram_mmu_el##_el(); \
Tony Xief6118cc2016-01-15 17:17:32 +080048 init_xlat_tables(); \
49 \
50 enable_mmu_el ## _el(0); \
51 }
52
53/* Define EL3 variants of the function initialising the MMU */
54DEFINE_CONFIGURE_MMU_EL(3)
55
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010056unsigned int plat_get_syscnt_freq2(void)
Tony Xief6118cc2016-01-15 17:17:32 +080057{
58 return SYS_COUNTER_FREQ_IN_TICKS;
59}
60
61void plat_cci_init(void)
62{
63#ifdef PLAT_RK_CCI_BASE
64 /* Initialize CCI driver */
65 cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
66#endif
67}
68
69void plat_cci_enable(void)
70{
71 /*
72 * Enable CCI coherency for this cluster.
73 * No need for locks as no other cpu is active at the moment.
74 */
75#ifdef PLAT_RK_CCI_BASE
76 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
77#endif
78}
79
80void plat_cci_disable(void)
81{
82#ifdef PLAT_RK_CCI_BASE
83 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
84#endif
85}