blob: 99274dec424108b2703901ade5f1e1edf26602ef [file] [log] [blame]
developer2189d3a2020-04-17 17:14:23 +08001/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10
11 .globl plat_is_my_cpu_primary
12 .globl plat_my_core_pos
13 .globl plat_mediatek_calc_core_pos
14
15func plat_is_my_cpu_primary
16 mrs x0, mpidr_el1
17 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
18 cmp x0, #PLAT_PRIMARY_CPU
19 cset x0, eq
20 ret
21endfunc plat_is_my_cpu_primary
22
23 /* -----------------------------------------------------
24 * unsigned int plat_my_core_pos(void)
25 * This function uses the plat_mediatek_calc_core_pos()
26 * definition to get the index of the calling CPU.
27 * -----------------------------------------------------
28 */
29func plat_my_core_pos
30 mrs x0, mpidr_el1
31 b plat_mediatek_calc_core_pos
32endfunc plat_my_core_pos
33
34 /* -----------------------------------------------------
35 * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
36 *
37 * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
38 * AFF0 is thread id. There is only one cluster in ARMv8.2
39 * and one thread in current implementation.
40 *
41 * With this function: CorePos = CoreID (AFF1)
42 * we do it with x0 = (x0 >> 8) & 0xff
43 * -----------------------------------------------------
44 */
45func plat_mediatek_calc_core_pos
46 mov x1, #MPIDR_AFFLVL_MASK
47 and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
48 ret
49endfunc plat_mediatek_calc_core_pos