Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 1 | /* |
Federico Recanati | fe09a42 | 2021-12-23 11:01:11 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 7 | #include <plat/arm/common/arm_config.h> |
| 8 | #include <plat/arm/common/plat_arm.h> |
Federico Recanati | fe09a42 | 2021-12-23 11:01:11 +0100 | [diff] [blame] | 9 | #include <platform_def.h> |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 10 | |
| 11 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 12 | * We assume that all security programming is done by the primary core. |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 13 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 14 | void plat_arm_security_setup(void) |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 15 | { |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 16 | /* |
| 17 | * The Base FVP has a TrustZone address space controller, the Foundation |
| 18 | * FVP does not. Trying to program the device on the foundation FVP will |
| 19 | * cause an abort. |
| 20 | * |
| 21 | * If the platform had additional peripheral specific security |
| 22 | * configurations, those would be configured here. |
| 23 | */ |
| 24 | |
Federico Recanati | fe09a42 | 2021-12-23 11:01:11 +0100 | [diff] [blame] | 25 | const arm_tzc_regions_info_t fvp_tzc_regions[] = { |
| 26 | ARM_TZC_REGIONS_DEF, |
| 27 | #if !SPM_MM && !ENABLE_RME |
| 28 | {FVP_DRAM3_BASE, FVP_DRAM3_END, |
| 29 | ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, |
| 30 | {FVP_DRAM4_BASE, FVP_DRAM4_END, |
| 31 | ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, |
| 32 | {FVP_DRAM5_BASE, FVP_DRAM5_END, |
| 33 | ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, |
| 34 | {FVP_DRAM6_BASE, FVP_DRAM6_END, |
| 35 | ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, |
| 36 | #endif |
| 37 | {0} |
| 38 | }; |
| 39 | |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 40 | if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U) |
Federico Recanati | fe09a42 | 2021-12-23 11:01:11 +0100 | [diff] [blame] | 41 | arm_tzc400_setup(PLAT_ARM_TZC_BASE, fvp_tzc_regions); |
Harry Liebel | cef9339 | 2014-04-01 19:27:38 +0100 | [diff] [blame] | 42 | } |