Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 8 | #include <assert.h> |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 9 | #include <debug.h> |
| 10 | #include <errno.h> |
| 11 | #include <hi6220.h> |
| 12 | #include <hi6553.h> |
| 13 | #include <mmio.h> |
| 14 | #include <sp804_delay_timer.h> |
| 15 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 16 | #include "hikey_private.h" |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 17 | |
| 18 | static void init_pll(void) |
| 19 | { |
| 20 | unsigned int data; |
| 21 | |
| 22 | data = mmio_read_32((0xf7032000 + 0x000)); |
| 23 | data |= 0x1; |
| 24 | mmio_write_32((0xf7032000 + 0x000), data); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 25 | do { |
| 26 | data = mmio_read_32((0xf7032000 + 0x000)); |
| 27 | } while (!(data & (1 << 28))); |
| 28 | |
| 29 | data = mmio_read_32((0xf7800000 + 0x000)); |
| 30 | data &= ~0x007; |
| 31 | data |= 0x004; |
| 32 | mmio_write_32((0xf7800000 + 0x000), data); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 33 | do { |
| 34 | data = mmio_read_32((0xf7800000 + 0x014)); |
| 35 | data &= 0x007; |
| 36 | } while (data != 0x004); |
| 37 | |
| 38 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 39 | dsb(); |
| 40 | isb(); |
| 41 | udelay(10); |
| 42 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); |
| 43 | dsb(); |
| 44 | isb(); |
| 45 | udelay(10); |
| 46 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); |
| 47 | dsb(); |
| 48 | isb(); |
| 49 | udelay(10); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 50 | mmio_write_32(0xf7032000 + 0x02c, 0x5110103e); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 51 | dsb(); |
| 52 | isb(); |
| 53 | udelay(10); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 54 | data = mmio_read_32(0xf7032000 + 0x050); |
| 55 | data |= 1 << 28; |
| 56 | mmio_write_32(0xf7032000 + 0x050, data); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 57 | dsb(); |
| 58 | isb(); |
| 59 | udelay(10); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 60 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 61 | dsb(); |
| 62 | isb(); |
| 63 | udelay(10); |
| 64 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2001); |
| 65 | dsb(); |
| 66 | isb(); |
| 67 | udelay(10); |
| 68 | mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2201); |
| 69 | dsb(); |
| 70 | isb(); |
| 71 | udelay(10); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | static void init_freq(void) |
| 75 | { |
| 76 | unsigned int data, tmp; |
| 77 | unsigned int cpuext_cfg, ddr_cfg; |
| 78 | |
| 79 | mmio_write_32((0xf7032000 + 0x374), 0x4a); |
| 80 | mmio_write_32((0xf7032000 + 0x368), 0xda); |
| 81 | mmio_write_32((0xf7032000 + 0x36c), 0x01); |
| 82 | mmio_write_32((0xf7032000 + 0x370), 0x01); |
| 83 | mmio_write_32((0xf7032000 + 0x360), 0x60); |
| 84 | mmio_write_32((0xf7032000 + 0x364), 0x60); |
| 85 | |
| 86 | mmio_write_32((0xf7032000 + 0x114), 0x1000); |
| 87 | |
| 88 | data = mmio_read_32((0xf7032000 + 0x110)); |
| 89 | data |= (3 << 12); |
| 90 | mmio_write_32((0xf7032000 + 0x110), data); |
| 91 | |
| 92 | data = mmio_read_32((0xf7032000 + 0x110)); |
| 93 | data |= (1 << 4); |
| 94 | mmio_write_32((0xf7032000 + 0x110), data); |
| 95 | |
| 96 | |
| 97 | data = mmio_read_32((0xf7032000 + 0x110)); |
| 98 | data &= ~0x7; |
| 99 | data |= 0x5; |
| 100 | mmio_write_32((0xf7032000 + 0x110), data); |
| 101 | dsb(); |
| 102 | mdelay(10); |
| 103 | |
| 104 | |
| 105 | do { |
| 106 | data = mmio_read_32((0xf6504000 + 0x008)); |
| 107 | data &= (3 << 20); |
| 108 | } while (data != (3 << 20)); |
| 109 | dsb(); |
| 110 | mdelay(10); |
| 111 | |
| 112 | |
| 113 | data = mmio_read_32((0xf6504000 + 0x054)); |
| 114 | data &= ~((1 << 0) | (1 << 11)); |
| 115 | mmio_write_32((0xf6504000 + 0x054), data); |
| 116 | mdelay(10); |
| 117 | |
| 118 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 119 | data &= ~(3 << 8); |
| 120 | data |= (1 << 8); |
| 121 | mmio_write_32((0xf7032000 + 0x104), data); |
| 122 | |
| 123 | data = mmio_read_32((0xf7032000 + 0x100)); |
| 124 | data |= (1 << 0); |
| 125 | mmio_write_32((0xf7032000 + 0x100), data); |
| 126 | dsb(); |
| 127 | |
| 128 | do { |
| 129 | data = mmio_read_32((0xf7032000 + 0x100)); |
| 130 | data &= (1 << 2); |
| 131 | } while (data != (1 << 2)); |
| 132 | |
| 133 | data = mmio_read_32((0xf6504000 + 0x06c)); |
| 134 | data &= ~0xffff; |
| 135 | data |= 0x56; |
| 136 | mmio_write_32((0xf6504000 + 0x06c), data); |
| 137 | |
| 138 | data = mmio_read_32((0xf6504000 + 0x06c)); |
| 139 | data &= ~(0xffffff << 8); |
| 140 | data |= 0xc7a << 8; |
| 141 | mmio_write_32((0xf6504000 + 0x06c), data); |
| 142 | |
| 143 | data = mmio_read_32((0xf6504000 + 0x058)); |
| 144 | data &= ((1 << 13) - 1); |
| 145 | data |= 0xccb; |
| 146 | mmio_write_32((0xf6504000 + 0x058), data); |
| 147 | |
| 148 | mmio_write_32((0xf6504000 + 0x060), 0x1fff); |
| 149 | mmio_write_32((0xf6504000 + 0x064), 0x1ffffff); |
| 150 | mmio_write_32((0xf6504000 + 0x068), 0x7fffffff); |
| 151 | mmio_write_32((0xf6504000 + 0x05c), 0x1); |
| 152 | |
| 153 | data = mmio_read_32((0xf6504000 + 0x054)); |
| 154 | data &= ~(0xf << 12); |
| 155 | data |= 1 << 12; |
| 156 | mmio_write_32((0xf6504000 + 0x054), data); |
| 157 | dsb(); |
| 158 | |
| 159 | |
| 160 | data = mmio_read_32((0xf7032000 + 0x000)); |
| 161 | data &= ~(1 << 0); |
| 162 | mmio_write_32((0xf7032000 + 0x000), data); |
| 163 | |
| 164 | mmio_write_32((0xf7032000 + 0x004), 0x5110207d); |
| 165 | mmio_write_32((0xf7032000 + 0x134), 0x10000005); |
| 166 | data = mmio_read_32((0xf7032000 + 0x134)); |
| 167 | |
| 168 | |
| 169 | data = mmio_read_32((0xf7032000 + 0x000)); |
| 170 | data |= (1 << 0); |
| 171 | mmio_write_32((0xf7032000 + 0x000), data); |
| 172 | |
| 173 | mmio_write_32((0xf7032000 + 0x368), 0x100da); |
| 174 | data = mmio_read_32((0xf7032000 + 0x378)); |
| 175 | data &= ~((1 << 7) - 1); |
| 176 | data |= 0x6b; |
| 177 | mmio_write_32((0xf7032000 + 0x378), data); |
| 178 | dsb(); |
| 179 | do { |
| 180 | data = mmio_read_32((0xf7032000 + 0x378)); |
| 181 | tmp = data & 0x7f; |
| 182 | data = (data & (0x7f << 8)) >> 8; |
| 183 | if (data != tmp) |
| 184 | continue; |
| 185 | data = mmio_read_32((0xf7032000 + 0x37c)); |
| 186 | } while (!(data & 1)); |
| 187 | |
| 188 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 189 | data &= ~((3 << 0) | |
| 190 | (3 << 8)); |
| 191 | cpuext_cfg = 1; |
| 192 | ddr_cfg = 1; |
| 193 | data |= cpuext_cfg | (ddr_cfg << 8); |
| 194 | mmio_write_32((0xf7032000 + 0x104), data); |
| 195 | dsb(); |
| 196 | |
| 197 | do { |
| 198 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 199 | tmp = (data & (3 << 16)) >> 16; |
| 200 | if (cpuext_cfg != tmp) |
| 201 | continue; |
| 202 | tmp = (data & (3 << 24)) >> 24; |
| 203 | if (ddr_cfg != tmp) |
| 204 | continue; |
| 205 | data = mmio_read_32((0xf7032000 + 0x000)); |
| 206 | data &= 1 << 28; |
| 207 | } while (!data); |
| 208 | |
| 209 | data = mmio_read_32((0xf7032000 + 0x100)); |
| 210 | data &= ~(1 << 0); |
| 211 | mmio_write_32((0xf7032000 + 0x100), data); |
| 212 | dsb(); |
| 213 | do { |
| 214 | data = mmio_read_32((0xf7032000 + 0x100)); |
| 215 | data &= (1 << 1); |
| 216 | } while (data != (1 << 1)); |
| 217 | mdelay(1000); |
| 218 | |
| 219 | data = mmio_read_32((0xf6504000 + 0x054)); |
| 220 | data &= ~(1 << 28); |
| 221 | mmio_write_32((0xf6504000 + 0x054), data); |
| 222 | dsb(); |
| 223 | |
| 224 | data = mmio_read_32((0xf7032000 + 0x110)); |
| 225 | data &= ~((1 << 4) | |
| 226 | (3 << 12)); |
| 227 | mmio_write_32((0xf7032000 + 0x110), data); |
| 228 | } |
| 229 | |
| 230 | int cat_533mhz_800mhz(void) |
| 231 | { |
| 232 | unsigned int data, i; |
| 233 | unsigned int bdl[5]; |
| 234 | |
| 235 | |
| 236 | data = mmio_read_32((0xf712c000 + 0x1c8)); |
| 237 | data &= 0xfffff0f0; |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 238 | data |= 0x100f01; |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 239 | mmio_write_32((0xf712c000 + 0x1c8), data); |
| 240 | |
| 241 | for (i = 0; i < 0x20; i++) { |
| 242 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 243 | data = (i << 0x10) + i; |
| 244 | mmio_write_32((0xf712c000 + 0x140), data); |
| 245 | mmio_write_32((0xf712c000 + 0x144), data); |
| 246 | mmio_write_32((0xf712c000 + 0x148), data); |
| 247 | mmio_write_32((0xf712c000 + 0x14c), data); |
| 248 | mmio_write_32((0xf712c000 + 0x150), data); |
| 249 | |
| 250 | |
| 251 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 252 | data |= 0x80000; |
| 253 | mmio_write_32((0xf712c000 + 0x070), data); |
| 254 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 255 | data &= 0xfff7ffff; |
| 256 | mmio_write_32((0xf712c000 + 0x070), data); |
| 257 | |
| 258 | |
| 259 | mmio_write_32((0xf712c000 + 0x004), 0x8000); |
| 260 | mmio_write_32((0xf712c000 + 0x004), 0x0); |
| 261 | mmio_write_32((0xf712c000 + 0x004), 0x801); |
| 262 | do { |
| 263 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 264 | } while (data & 1); |
| 265 | |
| 266 | data = mmio_read_32((0xf712c000 + 0x008)); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 267 | if ((data & 0x400) == 0) { |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 268 | mdelay(10); |
| 269 | return 0; |
| 270 | } |
| 271 | WARN("lpddr3 cat fail\n"); |
| 272 | data = mmio_read_32((0xf712c000 + 0x1d4)); |
| 273 | if ((data & 0x1f00) && ((data & 0x1f) == 0)) { |
| 274 | bdl[0] = mmio_read_32((0xf712c000 + 0x140)); |
| 275 | bdl[1] = mmio_read_32((0xf712c000 + 0x144)); |
| 276 | bdl[2] = mmio_read_32((0xf712c000 + 0x148)); |
| 277 | bdl[3] = mmio_read_32((0xf712c000 + 0x14c)); |
| 278 | bdl[4] = mmio_read_32((0xf712c000 + 0x150)); |
| 279 | if ((!(bdl[0] & 0x1f001f)) || (!(bdl[1] & 0x1f001f)) || |
| 280 | (!(bdl[2] & 0x1f001f)) || (!(bdl[3] & 0x1f001f)) || |
| 281 | (!(bdl[4] & 0x1f001f))) { |
| 282 | WARN("lpddr3 cat deskew error\n"); |
| 283 | if (i == 0x1f) { |
| 284 | WARN("addrnbdl is max\n"); |
| 285 | return -EINVAL; |
| 286 | } |
| 287 | mmio_write_32((0xf712c000 + 0x008), 0x400); |
| 288 | } else { |
| 289 | WARN("lpddr3 cat other error1\n"); |
| 290 | return -EINVAL; |
| 291 | } |
| 292 | } else { |
| 293 | WARN("lpddr3 cat other error2\n"); |
| 294 | return -EINVAL; |
| 295 | } |
| 296 | } |
| 297 | return -EINVAL; |
| 298 | } |
| 299 | |
| 300 | static void ddrx_rdet(void) |
| 301 | { |
| 302 | unsigned int data, rdet, bdl[4]; |
| 303 | |
| 304 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 305 | data &= 0xf800ffff; |
| 306 | data |= 0x8f0000; |
| 307 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 308 | |
| 309 | data = mmio_read_32((0xf712c000 + 0x0dc)); |
| 310 | data &= 0xfffffff0; |
| 311 | data |= 0xf; |
| 312 | mmio_write_32((0xf712c000 + 0x0dc), data); |
| 313 | |
| 314 | |
| 315 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 316 | data |= 0x80000; |
| 317 | mmio_write_32((0xf712c000 + 0x070), data); |
| 318 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 319 | data &= 0xfff7ffff; |
| 320 | mmio_write_32((0xf712c000 + 0x070), data); |
| 321 | |
| 322 | mmio_write_32((0xf712c000 + 0x004), 0x8000); |
| 323 | mmio_write_32((0xf712c000 + 0x004), 0); |
| 324 | |
| 325 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 326 | data &= ~0xf0000000; |
| 327 | data |= 0x80000000; |
| 328 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 329 | |
| 330 | mmio_write_32((0xf712c000 + 0x004), 0x101); |
| 331 | do { |
| 332 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 333 | } while (!(data & 1)); |
| 334 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 335 | if (data & 0x100) |
| 336 | WARN("rdet lbs fail\n"); |
| 337 | |
| 338 | bdl[0] = mmio_read_32((0xf712c000 + 0x22c)) & 0x7f; |
| 339 | bdl[1] = mmio_read_32((0xf712c000 + 0x2ac)) & 0x7f; |
| 340 | bdl[2] = mmio_read_32((0xf712c000 + 0x32c)) & 0x7f; |
| 341 | bdl[3] = mmio_read_32((0xf712c000 + 0x3ac)) & 0x7f; |
| 342 | do { |
| 343 | data = mmio_read_32((0xf712c000 + 0x22c)); |
| 344 | data &= ~0x7f; |
| 345 | data |= bdl[0]; |
| 346 | mmio_write_32((0xf712c000 + 0x22c), data); |
| 347 | data = mmio_read_32((0xf712c000 + 0x2ac)); |
| 348 | data &= ~0x7f; |
| 349 | data |= bdl[1]; |
| 350 | mmio_write_32((0xf712c000 + 0x2ac), data); |
| 351 | data = mmio_read_32((0xf712c000 + 0x32c)); |
| 352 | data &= ~0x7f; |
| 353 | data |= bdl[2]; |
| 354 | mmio_write_32((0xf712c000 + 0x32c), data); |
| 355 | data = mmio_read_32((0xf712c000 + 0x3ac)); |
| 356 | data &= ~0x7f; |
| 357 | data |= bdl[3]; |
| 358 | mmio_write_32((0xf712c000 + 0x3ac), data); |
| 359 | |
| 360 | |
| 361 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 362 | data |= 0x80000; |
| 363 | mmio_write_32((0xf712c000 + 0x070), data); |
| 364 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 365 | data &= 0xfff7ffff; |
| 366 | mmio_write_32((0xf712c000 + 0x070), data); |
| 367 | |
| 368 | mmio_write_32((0xf712c000 + 0x004), 0x8000); |
| 369 | mmio_write_32((0xf712c000 + 0x004), 0); |
| 370 | |
| 371 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 372 | data &= ~0xf0000000; |
| 373 | data |= 0x40000000; |
| 374 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 375 | mmio_write_32((0xf712c000 + 0x004), 0x101); |
| 376 | do { |
| 377 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 378 | } while (data & 1); |
| 379 | |
| 380 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 381 | rdet = data & 0x100; |
| 382 | if (rdet) { |
| 383 | INFO("rdet ds fail\n"); |
| 384 | mmio_write_32((0xf712c000 + 0x008), 0x100); |
| 385 | } |
| 386 | bdl[0]++; |
| 387 | bdl[1]++; |
| 388 | bdl[2]++; |
| 389 | bdl[3]++; |
| 390 | } while (rdet); |
| 391 | |
| 392 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 393 | data &= ~0xf0000000; |
| 394 | data |= 0x30000000; |
| 395 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 396 | |
| 397 | mmio_write_32((0xf712c000 + 0x004), 0x101); |
| 398 | do { |
| 399 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 400 | } while (data & 1); |
| 401 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 402 | if (data & 0x100) |
| 403 | INFO("rdet rbs av fail\n"); |
| 404 | } |
| 405 | |
| 406 | static void ddrx_wdet(void) |
| 407 | { |
Haojian Zhuang | 6ffe56c | 2017-05-31 12:42:10 +0800 | [diff] [blame] | 408 | unsigned int data, wdet, zero_bdl = 0, dq[4]; |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 409 | int i; |
| 410 | |
| 411 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 412 | data &= ~0xf; |
| 413 | data |= 0xf; |
| 414 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 415 | |
| 416 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 417 | data |= 0x80000; |
| 418 | mmio_write_32((0xf712c000 + 0x070), data); |
| 419 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 420 | data &= ~0x80000; |
| 421 | mmio_write_32((0xf712c000 + 0x070), data); |
| 422 | |
| 423 | mmio_write_32((0xf712c000 + 0x004), 0x8000); |
| 424 | mmio_write_32((0xf712c000 + 0x004), 0); |
| 425 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 426 | data &= ~0xf000; |
| 427 | data |= 0x8000; |
| 428 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 429 | mmio_write_32((0xf712c000 + 0x004), 0x201); |
| 430 | do { |
| 431 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 432 | } while (data & 1); |
| 433 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 434 | if (data & 0x200) |
| 435 | INFO("wdet lbs fail\n"); |
| 436 | |
| 437 | dq[0] = mmio_read_32((0xf712c000 + 0x234)) & 0x1f00; |
| 438 | dq[1] = mmio_read_32((0xf712c000 + 0x2b4)) & 0x1f00; |
| 439 | dq[2] = mmio_read_32((0xf712c000 + 0x334)) & 0x1f00; |
| 440 | dq[3] = mmio_read_32((0xf712c000 + 0x3b4)) & 0x1f00; |
| 441 | |
| 442 | do { |
| 443 | mmio_write_32((0xf712c000 + 0x234), dq[0]); |
| 444 | mmio_write_32((0xf712c000 + 0x2b4), dq[1]); |
| 445 | mmio_write_32((0xf712c000 + 0x334), dq[2]); |
| 446 | mmio_write_32((0xf712c000 + 0x3b4), dq[3]); |
| 447 | |
| 448 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 449 | data |= 0x80000; |
| 450 | mmio_write_32((0xf712c000 + 0x070), data); |
| 451 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 452 | data &= ~0x80000; |
| 453 | mmio_write_32((0xf712c000 + 0x070), data); |
| 454 | mmio_write_32((0xf712c000 + 0x004), 0x8000); |
| 455 | mmio_write_32((0xf712c000 + 0x004), 0); |
| 456 | |
| 457 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 458 | data &= ~0xf000; |
| 459 | data |= 0x4000; |
| 460 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 461 | mmio_write_32((0xf712c000 + 0x004), 0x201); |
| 462 | do { |
| 463 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 464 | } while (data & 1); |
| 465 | |
| 466 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 467 | wdet = data & 0x200; |
| 468 | if (wdet) { |
| 469 | INFO("wdet ds fail\n"); |
| 470 | mmio_write_32((0xf712c000 + 0x008), 0x200); |
| 471 | } |
| 472 | mdelay(10); |
| 473 | |
| 474 | for (i = 0; i < 4; i++) { |
| 475 | data = mmio_read_32((0xf712c000 + 0x210 + i * 0x80)); |
| 476 | if ((!(data & 0x1f)) || (!(data & 0x1f00)) || |
Haojian Zhuang | 6ffe56c | 2017-05-31 12:42:10 +0800 | [diff] [blame] | 477 | (!(data & 0x1f0000)) || (!(data & 0x1f000000))) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 478 | zero_bdl = 1; |
| 479 | data = mmio_read_32((0xf712c000 + 0x214 + i * 0x80)); |
| 480 | if ((!(data & 0x1f)) || (!(data & 0x1f00)) || |
Haojian Zhuang | 6ffe56c | 2017-05-31 12:42:10 +0800 | [diff] [blame] | 481 | (!(data & 0x1f0000)) || (!(data & 0x1f000000))) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 482 | zero_bdl = 1; |
| 483 | data = mmio_read_32((0xf712c000 + 0x218 + i * 0x80)); |
| 484 | if (!(data & 0x1f)) |
| 485 | zero_bdl = 1; |
| 486 | if (zero_bdl) { |
| 487 | if (i == 0) |
| 488 | dq[0] = dq[0] - 0x100; |
| 489 | if (i == 1) |
| 490 | dq[1] = dq[1] - 0x100; |
| 491 | if (i == 2) |
| 492 | dq[2] = dq[2] - 0x100; |
| 493 | if (i == 3) |
| 494 | dq[3] = dq[3] - 0x100; |
| 495 | } |
| 496 | } |
| 497 | } while (wdet); |
| 498 | |
| 499 | data = mmio_read_32((0xf712c000 + 0x0d0)); |
| 500 | data &= ~0xf000; |
| 501 | data |= 0x3000; |
| 502 | mmio_write_32((0xf712c000 + 0x0d0), data); |
| 503 | mmio_write_32((0xf712c000 + 0x004), 0x201); |
| 504 | do { |
| 505 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 506 | } while (data & 1); |
| 507 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 508 | if (data & 0x200) |
| 509 | INFO("wdet rbs av fail\n"); |
| 510 | } |
| 511 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 512 | void set_ddrc_150mhz(void) |
| 513 | { |
| 514 | unsigned int data; |
| 515 | |
| 516 | mmio_write_32((0xf7032000 + 0x580), 0x1); |
| 517 | mmio_write_32((0xf7032000 + 0x5a8), 0x7); |
| 518 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 519 | data &= 0xfffffcff; |
| 520 | mmio_write_32((0xf7032000 + 0x104), data); |
| 521 | |
| 522 | mmio_write_32((0xf7030000 + 0x050), 0x31); |
| 523 | mmio_write_32((0xf7030000 + 0x240), 0x5ffff); |
| 524 | mmio_write_32((0xf7030000 + 0x344), 0xf5ff); |
| 525 | mmio_write_32((0xf712c000 + 0x00c), 0x80000f0f); |
| 526 | mmio_write_32((0xf712c000 + 0x00c), 0xf0f); |
| 527 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 528 | mmio_write_32((0xf712c000 + 0x090), 0x7200000); |
| 529 | mmio_write_32((0xf712c000 + 0x258), 0x720); |
| 530 | mmio_write_32((0xf712c000 + 0x2d8), 0x720); |
| 531 | mmio_write_32((0xf712c000 + 0x358), 0x720); |
| 532 | mmio_write_32((0xf712c000 + 0x3d8), 0x720); |
| 533 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 534 | mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f); |
| 535 | mmio_write_32((0xf712c000 + 0x0b4), 0xf); |
| 536 | mmio_write_32((0xf712c000 + 0x088), 0x3fff801); |
| 537 | mmio_write_32((0xf712c000 + 0x070), 0x8940000); |
| 538 | |
| 539 | data = mmio_read_32((0xf712c000 + 0x078)); |
| 540 | data |= 4; |
| 541 | mmio_write_32((0xf712c000 + 0x078), data); |
| 542 | mmio_write_32((0xf712c000 + 0x01c), 0x8000080); |
| 543 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 544 | data &= 0xfffffffe; |
| 545 | mmio_write_32((0xf712c000 + 0x020), data); |
| 546 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 547 | mmio_write_32((0xf712c000 + 0x010), 0x500000f); |
| 548 | mmio_write_32((0xf712c000 + 0x014), 0x10); |
| 549 | data = mmio_read_32((0xf712c000 + 0x1e4)); |
| 550 | data &= 0xffffff00; |
| 551 | mmio_write_32((0xf712c000 + 0x1e4), data); |
| 552 | mmio_write_32((0xf712c000 + 0x030), 0x30c82355); |
| 553 | mmio_write_32((0xf712c000 + 0x034), 0x62112bb); |
| 554 | mmio_write_32((0xf712c000 + 0x038), 0x20041022); |
| 555 | mmio_write_32((0xf712c000 + 0x03c), 0x63177497); |
| 556 | mmio_write_32((0xf712c000 + 0x040), 0x3008407); |
| 557 | mmio_write_32((0xf712c000 + 0x064), 0x10483); |
| 558 | mmio_write_32((0xf712c000 + 0x068), 0xff0a0000); |
| 559 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 560 | data &= 0xffff0000; |
| 561 | data |= 0x184; |
| 562 | mmio_write_32((0xf712c000 + 0x070), data); |
| 563 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 564 | data &= 0xbfffffff; |
| 565 | mmio_write_32((0xf712c000 + 0x048), data); |
| 566 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 567 | data &= ~0x10; |
| 568 | mmio_write_32((0xf712c000 + 0x020), data); |
| 569 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 570 | data &= ~0x2000; |
| 571 | mmio_write_32((0xf712c000 + 0x080), data); |
| 572 | mmio_write_32((0xf712c000 + 0x270), 0x3); |
| 573 | mmio_write_32((0xf712c000 + 0x2f0), 0x3); |
| 574 | mmio_write_32((0xf712c000 + 0x370), 0x3); |
| 575 | mmio_write_32((0xf712c000 + 0x3f0), 0x3); |
| 576 | mmio_write_32((0xf712c000 + 0x048), 0x90420880); |
| 577 | |
| 578 | mmio_write_32((0xf7128000 + 0x040), 0x0); |
| 579 | mmio_write_32((0xf712c000 + 0x004), 0x146d); |
| 580 | mmio_write_32((0xf7128000 + 0x050), 0x100123); |
| 581 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 582 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 583 | mmio_write_32((0xf7128000 + 0x200), 0xa1000); |
| 584 | |
| 585 | mmio_write_32((0xf7128000 + 0x100), 0xb3290d08); |
| 586 | mmio_write_32((0xf7128000 + 0x104), 0x9621821); |
| 587 | mmio_write_32((0xf7128000 + 0x108), 0x45009023); |
| 588 | mmio_write_32((0xf7128000 + 0x10c), 0xaf44c145); |
| 589 | mmio_write_32((0xf7128000 + 0x110), 0x10b00000); |
| 590 | mmio_write_32((0xf7128000 + 0x114), 0x11080806); |
| 591 | mmio_write_32((0xf7128000 + 0x118), 0x44); |
| 592 | do { |
| 593 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 594 | } while (data & 1); |
| 595 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 596 | if (data & 8) { |
| 597 | NOTICE("fail to init ddr3 rank0\n"); |
| 598 | return; |
| 599 | } |
| 600 | |
| 601 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 602 | data |= 1; |
| 603 | mmio_write_32((0xf712c000 + 0x048), data); |
| 604 | mmio_write_32((0xf712c000 + 0x004), 0x21); |
| 605 | do { |
| 606 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 607 | } while (data & 1); |
| 608 | |
| 609 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 610 | if (data & 0x8) |
| 611 | NOTICE("ddr3 rank1 init failure\n"); |
| 612 | else |
| 613 | INFO("ddr3 rank1 init pass\n"); |
| 614 | |
| 615 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 616 | data &= ~0xf; |
| 617 | mmio_write_32((0xf712c000 + 0x048), data); |
| 618 | INFO("succeed to set ddrc 150mhz\n"); |
| 619 | } |
| 620 | |
| 621 | void set_ddrc_266mhz(void) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 622 | { |
| 623 | unsigned int data; |
| 624 | |
| 625 | mmio_write_32((0xf7032000 + 0x580), 0x3); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 626 | mmio_write_32((0xf7032000 + 0x5a8), 0x1003); |
| 627 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 628 | data &= 0xfffffcff; |
| 629 | mmio_write_32((0xf7032000 + 0x104), data); |
| 630 | |
| 631 | mmio_write_32((0xf7030000 + 0x050), 0x31); |
| 632 | mmio_write_32((0xf7030000 + 0x240), 0x5ffff); |
| 633 | mmio_write_32((0xf7030000 + 0x344), 0xf5ff); |
| 634 | mmio_write_32((0xf712c000 + 0x00c), 0x80000f0f); |
| 635 | mmio_write_32((0xf712c000 + 0x00c), 0xf0f); |
| 636 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 637 | mmio_write_32((0xf712c000 + 0x090), 0x7200000); |
| 638 | mmio_write_32((0xf712c000 + 0x258), 0x720); |
| 639 | mmio_write_32((0xf712c000 + 0x2d8), 0x720); |
| 640 | mmio_write_32((0xf712c000 + 0x358), 0x720); |
| 641 | mmio_write_32((0xf712c000 + 0x3d8), 0x720); |
| 642 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 643 | mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f); |
| 644 | mmio_write_32((0xf712c000 + 0x0b4), 0xf); |
| 645 | mmio_write_32((0xf712c000 + 0x088), 0x3fff801); |
| 646 | mmio_write_32((0xf712c000 + 0x070), 0x8940000); |
| 647 | |
| 648 | data = mmio_read_32((0xf712c000 + 0x078)); |
| 649 | data |= 4; |
| 650 | mmio_write_32((0xf712c000 + 0x078), data); |
| 651 | mmio_write_32((0xf712c000 + 0x01c), 0x8000080); |
| 652 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 653 | data &= 0xfffffffe; |
| 654 | mmio_write_32((0xf712c000 + 0x020), data); |
| 655 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 656 | mmio_write_32((0xf712c000 + 0x010), 0x500000f); |
| 657 | mmio_write_32((0xf712c000 + 0x014), 0x10); |
| 658 | data = mmio_read_32((0xf712c000 + 0x1e4)); |
| 659 | data &= 0xffffff00; |
| 660 | mmio_write_32((0xf712c000 + 0x1e4), data); |
| 661 | mmio_write_32((0xf712c000 + 0x030), 0x510d4455); |
| 662 | mmio_write_32((0xf712c000 + 0x034), 0x8391ebb); |
| 663 | mmio_write_32((0xf712c000 + 0x038), 0x2005103c); |
| 664 | mmio_write_32((0xf712c000 + 0x03c), 0x6329950b); |
| 665 | mmio_write_32((0xf712c000 + 0x040), 0x300858c); |
| 666 | mmio_write_32((0xf712c000 + 0x064), 0x10483); |
| 667 | mmio_write_32((0xf712c000 + 0x068), 0xff0a0000); |
| 668 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 669 | data &= 0xffff0000; |
| 670 | data |= 0x184; |
| 671 | mmio_write_32((0xf712c000 + 0x070), data); |
| 672 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 673 | data &= 0xbfffffff; |
| 674 | mmio_write_32((0xf712c000 + 0x048), data); |
| 675 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 676 | data &= ~0x10; |
| 677 | mmio_write_32((0xf712c000 + 0x020), data); |
| 678 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 679 | data &= ~0x2000; |
| 680 | mmio_write_32((0xf712c000 + 0x080), data); |
| 681 | mmio_write_32((0xf712c000 + 0x270), 0x3); |
| 682 | mmio_write_32((0xf712c000 + 0x2f0), 0x3); |
| 683 | mmio_write_32((0xf712c000 + 0x370), 0x3); |
| 684 | mmio_write_32((0xf712c000 + 0x3f0), 0x3); |
| 685 | mmio_write_32((0xf712c000 + 0x048), 0x90420880); |
| 686 | |
| 687 | mmio_write_32((0xf7128000 + 0x040), 0x0); |
| 688 | mmio_write_32((0xf712c000 + 0x004), 0x146d); |
| 689 | mmio_write_32((0xf7128000 + 0x050), 0x100123); |
| 690 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 691 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 692 | mmio_write_32((0xf7128000 + 0x200), 0xa1000); |
| 693 | |
| 694 | mmio_write_32((0xf7128000 + 0x100), 0xb441d50d); |
| 695 | mmio_write_32((0xf7128000 + 0x104), 0xf721839); |
| 696 | mmio_write_32((0xf7128000 + 0x108), 0x5500f03f); |
| 697 | mmio_write_32((0xf7128000 + 0x10c), 0xaf486145); |
| 698 | mmio_write_32((0xf7128000 + 0x110), 0x10b00000); |
| 699 | mmio_write_32((0xf7128000 + 0x114), 0x12080d06); |
| 700 | mmio_write_32((0xf7128000 + 0x118), 0x44); |
| 701 | do { |
| 702 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 703 | } while (data & 1); |
| 704 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 705 | if (data & 8) { |
| 706 | NOTICE("fail to init ddr3 rank0\n"); |
| 707 | return; |
| 708 | } |
| 709 | |
| 710 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 711 | data |= 1; |
| 712 | mmio_write_32((0xf712c000 + 0x048), data); |
| 713 | mmio_write_32((0xf712c000 + 0x004), 0x21); |
| 714 | do { |
| 715 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 716 | } while (data & 1); |
| 717 | |
| 718 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 719 | if (data & 0x8) |
| 720 | NOTICE("ddr3 rank1 init failure\n"); |
| 721 | else |
| 722 | INFO("ddr3 rank1 init pass\n"); |
| 723 | |
| 724 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 725 | data &= ~0xf; |
| 726 | mmio_write_32((0xf712c000 + 0x048), data); |
| 727 | INFO("succeed to set ddrc 266mhz\n"); |
| 728 | } |
| 729 | |
| 730 | void set_ddrc_400mhz(void) |
| 731 | { |
| 732 | unsigned int data; |
| 733 | |
| 734 | mmio_write_32((0xf7032000 + 0x580), 0x2); |
| 735 | mmio_write_32((0xf7032000 + 0x5a8), 0x1003); |
| 736 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 737 | data &= 0xfffffcff; |
| 738 | mmio_write_32((0xf7032000 + 0x104), data); |
| 739 | |
| 740 | mmio_write_32((0xf7030000 + 0x050), 0x31); |
| 741 | mmio_write_32((0xf7030000 + 0x240), 0x5ffff); |
| 742 | mmio_write_32((0xf7030000 + 0x344), 0xf5ff); |
| 743 | mmio_write_32((0xf712c000 + 0x00c), 0x80000f0f); |
| 744 | mmio_write_32((0xf712c000 + 0x00c), 0xf0f); |
| 745 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 746 | mmio_write_32((0xf712c000 + 0x090), 0x7200000); |
| 747 | mmio_write_32((0xf712c000 + 0x258), 0x720); |
| 748 | mmio_write_32((0xf712c000 + 0x2d8), 0x720); |
| 749 | mmio_write_32((0xf712c000 + 0x358), 0x720); |
| 750 | mmio_write_32((0xf712c000 + 0x3d8), 0x720); |
| 751 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 752 | mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f); |
| 753 | mmio_write_32((0xf712c000 + 0x0b4), 0xf); |
| 754 | mmio_write_32((0xf712c000 + 0x088), 0x3fff801); |
| 755 | mmio_write_32((0xf712c000 + 0x070), 0x8940000); |
| 756 | |
| 757 | data = mmio_read_32((0xf712c000 + 0x078)); |
| 758 | data |= 4; |
| 759 | mmio_write_32((0xf712c000 + 0x078), data); |
| 760 | mmio_write_32((0xf712c000 + 0x01c), 0x8000080); |
| 761 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 762 | data &= 0xfffffffe; |
| 763 | mmio_write_32((0xf712c000 + 0x020), data); |
| 764 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 765 | mmio_write_32((0xf712c000 + 0x010), 0x500000f); |
| 766 | mmio_write_32((0xf712c000 + 0x014), 0x10); |
| 767 | data = mmio_read_32((0xf712c000 + 0x1e4)); |
| 768 | data &= 0xffffff00; |
| 769 | mmio_write_32((0xf712c000 + 0x1e4), data); |
| 770 | mmio_write_32((0xf712c000 + 0x030), 0x75525655); |
| 771 | mmio_write_32((0xf712c000 + 0x034), 0xa552abb); |
| 772 | mmio_write_32((0xf712c000 + 0x038), 0x20071059); |
| 773 | mmio_write_32((0xf712c000 + 0x03c), 0x633e8591); |
| 774 | mmio_write_32((0xf712c000 + 0x040), 0x3008691); |
| 775 | mmio_write_32((0xf712c000 + 0x064), 0x10483); |
| 776 | mmio_write_32((0xf712c000 + 0x068), 0xff0a0000); |
| 777 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 778 | data &= 0xffff0000; |
| 779 | data |= 0x184; |
| 780 | mmio_write_32((0xf712c000 + 0x070), data); |
| 781 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 782 | data &= 0xbfffffff; |
| 783 | mmio_write_32((0xf712c000 + 0x048), data); |
| 784 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 785 | data &= ~0x10; |
| 786 | mmio_write_32((0xf712c000 + 0x020), data); |
| 787 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 788 | data &= ~0x2000; |
| 789 | mmio_write_32((0xf712c000 + 0x080), data); |
| 790 | mmio_write_32((0xf712c000 + 0x270), 0x3); |
| 791 | mmio_write_32((0xf712c000 + 0x2f0), 0x3); |
| 792 | mmio_write_32((0xf712c000 + 0x370), 0x3); |
| 793 | mmio_write_32((0xf712c000 + 0x3f0), 0x3); |
| 794 | mmio_write_32((0xf712c000 + 0x048), 0x90420880); |
| 795 | |
| 796 | mmio_write_32((0xf7128000 + 0x040), 0x0); |
| 797 | mmio_write_32((0xf712c000 + 0x004), 0x146d); |
| 798 | mmio_write_32((0xf7128000 + 0x050), 0x100123); |
| 799 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 800 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 801 | mmio_write_32((0xf7128000 + 0x200), 0xa1000); |
| 802 | |
| 803 | mmio_write_32((0xf7128000 + 0x100), 0xb55a9d12); |
| 804 | mmio_write_32((0xf7128000 + 0x104), 0x17721855); |
| 805 | mmio_write_32((0xf7128000 + 0x108), 0x7501505f); |
| 806 | mmio_write_32((0xf7128000 + 0x10c), 0xaf4ca245); |
| 807 | mmio_write_32((0xf7128000 + 0x110), 0x10b00000); |
| 808 | mmio_write_32((0xf7128000 + 0x114), 0x13081306); |
| 809 | mmio_write_32((0xf7128000 + 0x118), 0x44); |
| 810 | do { |
| 811 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 812 | } while (data & 1); |
| 813 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 814 | if (data & 8) { |
| 815 | NOTICE("fail to init ddr3 rank0\n"); |
| 816 | return; |
| 817 | } |
| 818 | |
| 819 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 820 | data |= 1; |
| 821 | mmio_write_32((0xf712c000 + 0x048), data); |
| 822 | mmio_write_32((0xf712c000 + 0x004), 0x21); |
| 823 | do { |
| 824 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 825 | } while (data & 1); |
| 826 | |
| 827 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 828 | if (data & 0x8) |
| 829 | NOTICE("ddr3 rank1 init failure\n"); |
| 830 | else |
| 831 | INFO("ddr3 rank1 init pass\n"); |
| 832 | |
| 833 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 834 | data &= ~0xf; |
| 835 | mmio_write_32((0xf712c000 + 0x048), data); |
| 836 | INFO("succeed to set ddrc 400mhz\n"); |
| 837 | } |
| 838 | |
| 839 | void set_ddrc_533mhz(void) |
| 840 | { |
| 841 | unsigned int data; |
| 842 | |
| 843 | mmio_write_32((0xf7032000 + 0x580), 0x3); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 844 | mmio_write_32((0xf7032000 + 0x5a8), 0x11111); |
| 845 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 846 | data |= 0x100; |
| 847 | mmio_write_32((0xf7032000 + 0x104), data); |
| 848 | |
| 849 | mmio_write_32((0xf7030000 + 0x050), 0x30); |
| 850 | mmio_write_32((0xf7030000 + 0x240), 0x5ffff); |
| 851 | mmio_write_32((0xf7030000 + 0x344), 0xf5ff); |
| 852 | mmio_write_32((0xf712c000 + 0x00c), 0x400); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 853 | mmio_write_32((0xf712c000 + 0x00c), 0x400); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 854 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 855 | mmio_write_32((0xf712c000 + 0x090), 0x6400000); |
| 856 | mmio_write_32((0xf712c000 + 0x258), 0x640); |
| 857 | mmio_write_32((0xf712c000 + 0x2d8), 0x640); |
| 858 | mmio_write_32((0xf712c000 + 0x358), 0x640); |
| 859 | mmio_write_32((0xf712c000 + 0x3d8), 0x640); |
| 860 | mmio_write_32((0xf712c000 + 0x018), 0x0); |
| 861 | mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f); |
| 862 | mmio_write_32((0xf712c000 + 0x0b4), 0xf); |
| 863 | mmio_write_32((0xf712c000 + 0x088), 0x3fff801); |
| 864 | mmio_write_32((0xf712c000 + 0x070), 0x8940000); |
| 865 | |
| 866 | data = mmio_read_32((0xf712c000 + 0x078)); |
| 867 | data |= 4; |
| 868 | mmio_write_32((0xf712c000 + 0x078), data); |
| 869 | mmio_write_32((0xf712c000 + 0x01c), 0x8000080); |
| 870 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 871 | data &= 0xfffffffe; |
| 872 | mmio_write_32((0xf712c000 + 0x020), data); |
| 873 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 874 | mmio_write_32((0xf712c000 + 0x010), 0x500000f); |
| 875 | mmio_write_32((0xf712c000 + 0x014), 0x10); |
| 876 | data = mmio_read_32((0xf712c000 + 0x1e4)); |
| 877 | data &= 0xffffff00; |
| 878 | mmio_write_32((0xf712c000 + 0x1e4), data); |
| 879 | mmio_write_32((0xf712c000 + 0x030), 0x9dd87855); |
| 880 | mmio_write_32((0xf712c000 + 0x034), 0xa7138bb); |
| 881 | mmio_write_32((0xf712c000 + 0x038), 0x20091477); |
| 882 | mmio_write_32((0xf712c000 + 0x03c), 0x84534e16); |
| 883 | mmio_write_32((0xf712c000 + 0x040), 0x3008817); |
| 884 | mmio_write_32((0xf712c000 + 0x064), 0x106c3); |
| 885 | mmio_write_32((0xf712c000 + 0x068), 0xff0a0000); |
| 886 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 887 | data &= 0xffff0000; |
| 888 | data |= 0x305; |
| 889 | mmio_write_32((0xf712c000 + 0x070), data); |
| 890 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 891 | data |= 0x40000000; |
| 892 | mmio_write_32((0xf712c000 + 0x048), data); |
| 893 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 894 | data &= ~0x10; |
| 895 | mmio_write_32((0xf712c000 + 0x020), data); |
| 896 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 897 | data &= ~0x2000; |
| 898 | mmio_write_32((0xf712c000 + 0x080), data); |
| 899 | mmio_write_32((0xf712c000 + 0x270), 0x3); |
| 900 | mmio_write_32((0xf712c000 + 0x2f0), 0x3); |
| 901 | mmio_write_32((0xf712c000 + 0x370), 0x3); |
| 902 | mmio_write_32((0xf712c000 + 0x3f0), 0x3); |
| 903 | mmio_write_32((0xf712c000 + 0x048), 0xd0420900); |
| 904 | |
| 905 | mmio_write_32((0xf7128000 + 0x040), 0x0); |
| 906 | mmio_write_32((0xf712c000 + 0x004), 0x140f); |
| 907 | do { |
| 908 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 909 | } while (data & 1); |
| 910 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 911 | if (data & 0x7fe) { |
| 912 | NOTICE("failed to init lpddr3 rank0 dram phy\n"); |
| 913 | return; |
| 914 | } |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 915 | cat_533mhz_800mhz(); |
| 916 | |
| 917 | mmio_write_32((0xf712c000 + 0x004), 0xf1); |
| 918 | mmio_write_32((0xf7128000 + 0x050), 0x100123); |
| 919 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 920 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 921 | mmio_write_32((0xf7128000 + 0x200), 0xa1000); |
| 922 | |
| 923 | mmio_write_32((0xf7128000 + 0x100), 0xb77b6718); |
| 924 | mmio_write_32((0xf7128000 + 0x104), 0x1e82a071); |
| 925 | mmio_write_32((0xf7128000 + 0x108), 0x9501c07e); |
| 926 | mmio_write_32((0xf7128000 + 0x10c), 0xaf50c255); |
| 927 | mmio_write_32((0xf7128000 + 0x110), 0x10b00000); |
| 928 | mmio_write_32((0xf7128000 + 0x114), 0x13181908); |
| 929 | mmio_write_32((0xf7128000 + 0x118), 0x44); |
| 930 | do { |
| 931 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 932 | } while (data & 1); |
| 933 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 934 | if (data & 0x7fe) { |
| 935 | NOTICE("fail to init ddr3 rank0\n"); |
| 936 | return; |
| 937 | } |
| 938 | ddrx_rdet(); |
| 939 | ddrx_wdet(); |
| 940 | |
| 941 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 942 | data |= 1; |
| 943 | mmio_write_32((0xf712c000 + 0x048), data); |
| 944 | mmio_write_32((0xf712c000 + 0x004), 0x21); |
| 945 | do { |
| 946 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 947 | } while (data & 1); |
| 948 | |
| 949 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 950 | if (data & 0x7fe) |
| 951 | NOTICE("ddr3 rank1 init failure\n"); |
| 952 | else |
| 953 | INFO("ddr3 rank1 init pass\n"); |
| 954 | |
| 955 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 956 | data &= ~0xf; |
| 957 | mmio_write_32((0xf712c000 + 0x048), data); |
| 958 | INFO("succeed to set ddrc 533mhz\n"); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 959 | } |
| 960 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 961 | void set_ddrc_800mhz(void) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 962 | { |
| 963 | unsigned int data; |
| 964 | |
| 965 | mmio_write_32((0xf7032000 + 0x580), 0x2); |
| 966 | mmio_write_32((0xf7032000 + 0x5a8), 0x1003); |
| 967 | data = mmio_read_32((0xf7032000 + 0x104)); |
| 968 | data &= 0xfffffcff; |
| 969 | mmio_write_32((0xf7032000 + 0x104), data); |
| 970 | |
| 971 | mmio_write_32((0xf7030000 + 0x050), 0x30); |
| 972 | mmio_write_32((0xf7030000 + 0x240), 0x5ffff); |
| 973 | mmio_write_32((0xf7030000 + 0x344), 0xf5ff); |
| 974 | mmio_write_32((0xf712c000 + 0x00c), 0x400); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 975 | mmio_write_32((0xf712c000 + 0x00c), 0x400); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 976 | mmio_write_32((0xf712c000 + 0x018), 0x7); |
| 977 | mmio_write_32((0xf712c000 + 0x090), 0x5400000); |
| 978 | mmio_write_32((0xf712c000 + 0x258), 0x540); |
| 979 | mmio_write_32((0xf712c000 + 0x2d8), 0x540); |
| 980 | mmio_write_32((0xf712c000 + 0x358), 0x540); |
| 981 | mmio_write_32((0xf712c000 + 0x3d8), 0x540); |
| 982 | mmio_write_32((0xf712c000 + 0x018), 0x0); |
| 983 | mmio_write_32((0xf712c000 + 0x0b0), 0xf00000f); |
| 984 | mmio_write_32((0xf712c000 + 0x0b4), 0xf); |
| 985 | mmio_write_32((0xf712c000 + 0x088), 0x3fff801); |
| 986 | mmio_write_32((0xf712c000 + 0x070), 0x8940000); |
| 987 | |
| 988 | data = mmio_read_32((0xf712c000 + 0x078)); |
| 989 | data |= 4; |
| 990 | mmio_write_32((0xf712c000 + 0x078), data); |
| 991 | mmio_write_32((0xf712c000 + 0x01c), 0x8000080); |
| 992 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 993 | data &= 0xfffffffe; |
| 994 | mmio_write_32((0xf712c000 + 0x020), data); |
| 995 | mmio_write_32((0xf712c000 + 0x1d4), 0xc0000); |
| 996 | mmio_write_32((0xf712c000 + 0x010), 0x500000f); |
| 997 | mmio_write_32((0xf712c000 + 0x014), 0x10); |
| 998 | data = mmio_read_32((0xf712c000 + 0x1e4)); |
| 999 | data &= 0xffffff00; |
| 1000 | mmio_write_32((0xf712c000 + 0x1e4), data); |
| 1001 | mmio_write_32((0xf712c000 + 0x030), 0xe663ab77); |
| 1002 | mmio_write_32((0xf712c000 + 0x034), 0xea952db); |
| 1003 | mmio_write_32((0xf712c000 + 0x038), 0x200d1cb1); |
| 1004 | mmio_write_32((0xf712c000 + 0x03c), 0xc67d0721); |
| 1005 | mmio_write_32((0xf712c000 + 0x040), 0x3008aa1); |
| 1006 | mmio_write_32((0xf712c000 + 0x064), 0x11a43); |
| 1007 | mmio_write_32((0xf712c000 + 0x068), 0xff0a0000); |
| 1008 | data = mmio_read_32((0xf712c000 + 0x070)); |
| 1009 | data &= 0xffff0000; |
| 1010 | data |= 0x507; |
| 1011 | mmio_write_32((0xf712c000 + 0x070), data); |
| 1012 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 1013 | data |= 0x40000000; |
| 1014 | mmio_write_32((0xf712c000 + 0x048), data); |
| 1015 | data = mmio_read_32((0xf712c000 + 0x020)); |
| 1016 | data &= 0xffffffef; |
| 1017 | mmio_write_32((0xf712c000 + 0x020), data); |
| 1018 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 1019 | data &= 0xffffdfff; |
| 1020 | mmio_write_32((0xf712c000 + 0x080), data); |
| 1021 | mmio_write_32((0xf712c000 + 0x270), 0x3); |
| 1022 | mmio_write_32((0xf712c000 + 0x2f0), 0x3); |
| 1023 | mmio_write_32((0xf712c000 + 0x370), 0x3); |
| 1024 | mmio_write_32((0xf712c000 + 0x3f0), 0x3); |
| 1025 | mmio_write_32((0xf712c000 + 0x048), 0xd0420900); |
| 1026 | |
| 1027 | mmio_write_32((0xf7128000 + 0x040), 0x2001); |
| 1028 | mmio_write_32((0xf712c000 + 0x004), 0x140f); |
| 1029 | do { |
| 1030 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 1031 | } while (data & 1); |
| 1032 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 1033 | if (data & 0x7fe) { |
| 1034 | WARN("failed to init lpddr3 rank0 dram phy\n"); |
| 1035 | return; |
| 1036 | } |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1037 | cat_533mhz_800mhz(); |
| 1038 | |
| 1039 | mmio_write_32((0xf712c000 + 0x004), 0xf1); |
| 1040 | mmio_write_32((0xf7128000 + 0x050), 0x100023); |
| 1041 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 1042 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 1043 | mmio_write_32((0xf7128000 + 0x200), 0xa1000); |
| 1044 | |
| 1045 | mmio_write_32((0xf7128000 + 0x100), 0x755a9d12); |
| 1046 | mmio_write_32((0xf7128000 + 0x104), 0x1753b055); |
| 1047 | mmio_write_32((0xf7128000 + 0x108), 0x7401505f); |
| 1048 | mmio_write_32((0xf7128000 + 0x10c), 0x578ca244); |
| 1049 | mmio_write_32((0xf7128000 + 0x110), 0x10700000); |
| 1050 | mmio_write_32((0xf7128000 + 0x114), 0x13141306); |
| 1051 | mmio_write_32((0xf7128000 + 0x118), 0x44); |
| 1052 | do { |
| 1053 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 1054 | } while (data & 1); |
| 1055 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 1056 | if (data & 0x7fe) { |
| 1057 | NOTICE("fail to init ddr3 rank0\n"); |
| 1058 | return; |
| 1059 | } |
| 1060 | ddrx_rdet(); |
| 1061 | ddrx_wdet(); |
| 1062 | |
| 1063 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 1064 | data |= 1; |
| 1065 | mmio_write_32((0xf712c000 + 0x048), data); |
| 1066 | mmio_write_32((0xf712c000 + 0x004), 0x21); |
| 1067 | do { |
| 1068 | data = mmio_read_32((0xf712c000 + 0x004)); |
| 1069 | } while (data & 1); |
| 1070 | |
| 1071 | data = mmio_read_32((0xf712c000 + 0x008)); |
| 1072 | if (data & 0x7fe) |
| 1073 | NOTICE("ddr3 rank1 init failure\n"); |
| 1074 | else |
| 1075 | INFO("ddr3 rank1 init pass\n"); |
| 1076 | |
| 1077 | data = mmio_read_32((0xf712c000 + 0x048)); |
| 1078 | data &= ~0xf; |
| 1079 | mmio_write_32((0xf712c000 + 0x048), data); |
| 1080 | INFO("succeed to set ddrc 800mhz\n"); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1081 | } |
| 1082 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1083 | static void ddrc_common_init(int freq) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1084 | { |
| 1085 | unsigned int data; |
| 1086 | |
| 1087 | mmio_write_32((0xf7120000 + 0x020), 0x1); |
| 1088 | mmio_write_32((0xf7120000 + 0x100), 0x1700); |
| 1089 | mmio_write_32((0xf7120000 + 0x104), 0x71040004); |
| 1090 | mmio_write_32((0xf7121400 + 0x104), 0xf); |
| 1091 | mmio_write_32((0xf7121800 + 0x104), 0xf); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1092 | mmio_write_32((0xf7121c00 + 0x104), 0xf); |
| 1093 | mmio_write_32((0xf7122000 + 0x104), 0xf); |
| 1094 | mmio_write_32((0xf7128000 + 0x02c), 0x6); |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1095 | mmio_write_32((0xf7128000 + 0x020), 0x30003); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1096 | mmio_write_32((0xf7128000 + 0x028), 0x310201); |
| 1097 | mmio_write_32((0xf712c000 + 0x1e4), 0xfe007600); |
| 1098 | mmio_write_32((0xf7128000 + 0x01c), 0xaf001); |
| 1099 | |
| 1100 | |
| 1101 | data = mmio_read_32((0xf7128000 + 0x280)); |
| 1102 | data |= 1 << 7; |
| 1103 | mmio_write_32((0xf7128000 + 0x280), data); |
| 1104 | mmio_write_32((0xf7128000 + 0x244), 0x3); |
| 1105 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1106 | if (freq == DDR_FREQ_800M) |
| 1107 | mmio_write_32((0xf7128000 + 0x240), 167 * (freq / 2) / 1024); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1108 | else |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1109 | mmio_write_32((0xf7128000 + 0x240), 167 * freq / 1024); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1110 | |
| 1111 | data = mmio_read_32((0xf712c000 + 0x080)); |
| 1112 | data &= 0xffff; |
| 1113 | data |= 0x4002000; |
| 1114 | mmio_write_32((0xf712c000 + 0x080), data); |
| 1115 | mmio_write_32((0xf7128000 + 0x000), 0x0); |
| 1116 | do { |
| 1117 | data = mmio_read_32((0xf7128000 + 0x294)); |
| 1118 | } while (data & 1); |
| 1119 | mmio_write_32((0xf7128000 + 0x000), 0x2); |
| 1120 | } |
| 1121 | |
| 1122 | |
| 1123 | static int dienum_det_and_rowcol_cfg(void) |
| 1124 | { |
| 1125 | unsigned int data; |
| 1126 | |
| 1127 | mmio_write_32((0xf7128000 + 0x210), 0x87); |
| 1128 | mmio_write_32((0xf7128000 + 0x218), 0x10000); |
| 1129 | mmio_write_32((0xf7128000 + 0x00c), 0x1); |
| 1130 | do { |
| 1131 | data = mmio_read_32((0xf7128000 + 0x00c)); |
| 1132 | } while (data & 1); |
| 1133 | data = mmio_read_32((0xf7128000 + 0x4a8)) & 0xfc; |
| 1134 | switch (data) { |
| 1135 | case 0x18: |
| 1136 | mmio_write_32((0xf7128000 + 0x060), 0x132); |
| 1137 | mmio_write_32((0xf7128000 + 0x064), 0x132); |
| 1138 | mmio_write_32((0xf7120000 + 0x100), 0x1600); |
| 1139 | mmio_write_32((0xf7120000 + 0x104), 0x71040004); |
| 1140 | break; |
| 1141 | case 0x1c: |
| 1142 | mmio_write_32((0xf7128000 + 0x060), 0x142); |
| 1143 | mmio_write_32((0xf7128000 + 0x064), 0x142); |
| 1144 | mmio_write_32((0xf7120000 + 0x100), 0x1700); |
| 1145 | mmio_write_32((0xf7120000 + 0x104), 0x71040004); |
| 1146 | break; |
| 1147 | case 0x58: |
| 1148 | mmio_write_32((0xf7128000 + 0x060), 0x133); |
| 1149 | mmio_write_32((0xf7128000 + 0x064), 0x133); |
| 1150 | mmio_write_32((0xf7120000 + 0x100), 0x1700); |
| 1151 | mmio_write_32((0xf7120000 + 0x104), 0x71040004); |
| 1152 | break; |
| 1153 | default: |
| 1154 | break; |
| 1155 | } |
| 1156 | if (!data) |
| 1157 | return -EINVAL; |
| 1158 | return 0; |
| 1159 | } |
| 1160 | |
| 1161 | static int detect_ddr_chip_info(void) |
| 1162 | { |
| 1163 | unsigned int data, mr5, mr6, mr7; |
| 1164 | |
| 1165 | mmio_write_32((0xf7128000 + 0x210), 0x57); |
| 1166 | mmio_write_32((0xf7128000 + 0x218), 0x10000); |
| 1167 | mmio_write_32((0xf7128000 + 0x00c), 0x1); |
| 1168 | |
| 1169 | do { |
| 1170 | data = mmio_read_32((0xf7128000 + 0x00c)); |
| 1171 | } while (data & 1); |
| 1172 | |
| 1173 | data = mmio_read_32((0xf7128000 + 0x4a8)); |
| 1174 | mr5 = data & 0xff; |
| 1175 | switch (mr5) { |
| 1176 | case 1: |
| 1177 | INFO("Samsung DDR\n"); |
| 1178 | break; |
| 1179 | case 6: |
| 1180 | INFO("Hynix DDR\n"); |
| 1181 | break; |
| 1182 | case 3: |
| 1183 | INFO("Elpida DDR\n"); |
| 1184 | break; |
| 1185 | default: |
| 1186 | INFO("DDR from other vendors\n"); |
| 1187 | break; |
| 1188 | } |
| 1189 | |
| 1190 | mmio_write_32((0xf7128000 + 0x210), 0x67); |
| 1191 | mmio_write_32((0xf7128000 + 0x218), 0x10000); |
| 1192 | mmio_write_32((0xf7128000 + 0x00c), 0x1); |
| 1193 | do { |
| 1194 | data = mmio_read_32((0xf7128000 + 0x00c)); |
| 1195 | } while (data & 1); |
| 1196 | data = mmio_read_32((0xf7128000 + 0x4a8)); |
| 1197 | mr6 = data & 0xff; |
| 1198 | mmio_write_32((0xf7128000 + 0x210), 0x77); |
| 1199 | mmio_write_32((0xf7128000 + 0x218), 0x10000); |
| 1200 | mmio_write_32((0xf7128000 + 0x00c), 0x1); |
| 1201 | do { |
| 1202 | data = mmio_read_32((0xf7128000 + 0x00c)); |
| 1203 | } while (data & 1); |
| 1204 | data = mmio_read_32((0xf7128000 + 0x4a8)); |
| 1205 | mr7 = data & 0xff; |
| 1206 | data = mr5 + (mr6 << 8) + (mr7 << 16); |
| 1207 | return data; |
| 1208 | } |
| 1209 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1210 | void ddr_phy_reset(void) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1211 | { |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1212 | mmio_write_32(0xf7030340, 0xa000); |
| 1213 | mmio_write_32(0xf7030344, 0xa000); |
| 1214 | } |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1215 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1216 | int lpddr3_freq_init(int freq) |
| 1217 | { |
| 1218 | set_ddrc_150mhz(); |
| 1219 | if (freq > DDR_FREQ_150M) { |
| 1220 | ddr_phy_reset(); |
| 1221 | set_ddrc_266mhz(); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1222 | } |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1223 | if (freq > DDR_FREQ_266M) { |
| 1224 | ddr_phy_reset(); |
| 1225 | set_ddrc_400mhz(); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1226 | } |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1227 | if (freq > DDR_FREQ_400M) { |
| 1228 | ddr_phy_reset(); |
| 1229 | set_ddrc_533mhz(); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1230 | } |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1231 | if (freq > DDR_FREQ_533M) { |
| 1232 | ddr_phy_reset(); |
| 1233 | set_ddrc_800mhz(); |
| 1234 | } |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1235 | return 0; |
| 1236 | } |
| 1237 | |
| 1238 | static void init_ddr(int freq) |
| 1239 | { |
| 1240 | unsigned int data; |
| 1241 | int ret; |
| 1242 | |
| 1243 | |
| 1244 | data = mmio_read_32((0xf7032000 + 0x030)); |
| 1245 | data |= 1; |
| 1246 | mmio_write_32((0xf7032000 + 0x030), data); |
| 1247 | data = mmio_read_32((0xf7032000 + 0x010)); |
| 1248 | data |= 1; |
| 1249 | mmio_write_32((0xf7032000 + 0x010), data); |
| 1250 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1251 | udelay(300); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1252 | do { |
| 1253 | data = mmio_read_32((0xf7032000 + 0x030)); |
| 1254 | data &= 3 << 28; |
| 1255 | } while (data != (3 << 28)); |
| 1256 | do { |
| 1257 | data = mmio_read_32((0xf7032000 + 0x010)); |
| 1258 | data &= 3 << 28; |
| 1259 | } while (data != (3 << 28)); |
| 1260 | |
| 1261 | ret = lpddr3_freq_init(freq); |
| 1262 | if (ret) |
| 1263 | return; |
| 1264 | } |
| 1265 | |
| 1266 | static void init_ddrc_qos(void) |
| 1267 | { |
| 1268 | unsigned int port, data; |
| 1269 | |
| 1270 | mmio_write_32((0xf7124000 + 0x088), 1); |
| 1271 | |
| 1272 | port = 0; |
| 1273 | mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); |
| 1274 | mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x11111111); |
| 1275 | mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x11111111); |
| 1276 | mmio_write_32((0xf7120000 + 0x400 + 0 * 0x10), 0x001d0007); |
| 1277 | |
| 1278 | for (port = 3; port <= 4; port++) { |
| 1279 | mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); |
| 1280 | mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x77777777); |
| 1281 | mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x77777777); |
| 1282 | } |
| 1283 | |
| 1284 | port = 1; |
| 1285 | mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000); |
| 1286 | mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567); |
| 1287 | mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567); |
| 1288 | |
| 1289 | mmio_write_32((0xf7124000 + 0x1f0), 0); |
| 1290 | mmio_write_32((0xf7124000 + 0x0bc), 0x3020100); |
| 1291 | mmio_write_32((0xf7124000 + 0x0d0), 0x3020100); |
| 1292 | mmio_write_32((0xf7124000 + 0x1f4), 0x01000100); |
| 1293 | mmio_write_32((0xf7124000 + 0x08c + 0 * 4), 0xd0670402); |
| 1294 | mmio_write_32((0xf7124000 + 0x068 + 0 * 4), 0x31); |
| 1295 | mmio_write_32((0xf7124000 + 0x000), 0x7); |
| 1296 | |
| 1297 | data = mmio_read_32((0xf7124000 + 0x09c)); |
| 1298 | data &= ~0xff0000; |
| 1299 | data |= 0x400000; |
| 1300 | mmio_write_32((0xf7124000 + 0x09c), data); |
| 1301 | data = mmio_read_32((0xf7124000 + 0x0ac)); |
| 1302 | data &= ~0xff0000; |
| 1303 | data |= 0x400000; |
| 1304 | mmio_write_32((0xf7124000 + 0x0ac), data); |
| 1305 | port = 2; |
| 1306 | mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000); |
| 1307 | mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567); |
| 1308 | mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567); |
| 1309 | |
| 1310 | |
| 1311 | mmio_write_32((0xf7124000 + 0x09c), 0xff7fff); |
| 1312 | mmio_write_32((0xf7124000 + 0x0a0), 0xff); |
| 1313 | mmio_write_32((0xf7124000 + 0x0ac), 0xff7fff); |
| 1314 | mmio_write_32((0xf7124000 + 0x0b0), 0xff); |
| 1315 | mmio_write_32((0xf7124000 + 0x0bc), 0x3020100); |
| 1316 | mmio_write_32((0xf7124000 + 0x0d0), 0x3020100); |
| 1317 | } |
| 1318 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1319 | void hikey_ddr_init(unsigned int ddr_freq) |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1320 | { |
| 1321 | uint32_t data; |
| 1322 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1323 | assert((ddr_freq == DDR_FREQ_150M) || (ddr_freq == DDR_FREQ_266M) || |
| 1324 | (ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_533M) || |
| 1325 | (ddr_freq == DDR_FREQ_800M)); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1326 | init_pll(); |
| 1327 | init_freq(); |
| 1328 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1329 | init_ddr(ddr_freq); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1330 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1331 | ddrc_common_init(ddr_freq); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1332 | dienum_det_and_rowcol_cfg(); |
| 1333 | detect_ddr_chip_info(); |
| 1334 | |
Haojian Zhuang | e18de67 | 2018-04-11 19:05:32 +0800 | [diff] [blame^] | 1335 | if ((ddr_freq == DDR_FREQ_400M) || (ddr_freq == DDR_FREQ_800M)) { |
| 1336 | data = mmio_read_32(0xf7032000 + 0x010); |
| 1337 | data &= ~0x1; |
| 1338 | mmio_write_32(0xf7032000 + 0x010, data); |
| 1339 | } else if ((ddr_freq == DDR_FREQ_266M) || (ddr_freq == DDR_FREQ_533M)) { |
| 1340 | data = mmio_read_32(0xf7032000 + 0x030); |
| 1341 | data &= ~0x1; |
| 1342 | mmio_write_32(0xf7032000 + 0x030, data); |
| 1343 | } else { |
| 1344 | data = mmio_read_32(0xf7032000 + 0x010); |
| 1345 | data &= ~0x1; |
| 1346 | mmio_write_32(0xf7032000 + 0x010, data); |
| 1347 | data = mmio_read_32(0xf7032000 + 0x030); |
| 1348 | data &= ~0x1; |
| 1349 | mmio_write_32(0xf7032000 + 0x030, data); |
| 1350 | } |
| 1351 | dsb(); |
| 1352 | isb(); |
Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1353 | |
| 1354 | /* |
| 1355 | * Test memory access. Do not use address 0x0 because the compiler |
| 1356 | * may assume it is not a valid address and generate incorrect code |
| 1357 | * (GCC 4.9.1 without -fno-delete-null-pointer-checks for instance). |
| 1358 | */ |
| 1359 | mmio_write_32(0x4, 0xa5a55a5a); |
| 1360 | INFO("ddr test value:0x%x\n", mmio_read_32(0x4)); |
| 1361 | init_ddrc_qos(); |
| 1362 | } |