blob: eb2db33b7772695440b2d0a4ac69178f43c11d79 [file] [log] [blame]
jason-ch chenfa82b9b2021-11-16 09:48:20 +08001/*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PCM_DEF_H
8#define PCM_DEF_H
9
10/*
11 * Auto generated by DE, please DO NOT modify this file directly.
12 */
13
14/* --- R0 Define --- */
15#define R0_SC_26M_CK_OFF (1U << 0)
16#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
17#define R0_SC_MEM_CK_OFF (1U << 2)
18#define R0_SC_AXI_CK_OFF (1U << 3)
19#define R0_SC_DR_SRAM_LOAD (1U << 4)
20#define R0_SC_MD26M_CK_OFF (1U << 5)
21#define R0_SC_DPY_MODE_SW (1U << 6)
22#define R0_SC_DMSUS_OFF (1U << 7)
23#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
24#define R0_SC_DR_SRAM_RESTORE (1U << 9)
25#define R0_SC_MPLLOUT_OFF (1U << 10)
26#define R0_SC_TX_TRACKING_DIS (1U << 11)
27#define R0_SC_DPY_DLL_EN (1U << 12)
28#define R0_SC_DPY_DLL_CK_EN (1U << 13)
29#define R0_SC_DPY_VREF_EN (1U << 14)
30#define R0_SC_PHYPLL_EN (1U << 15)
31#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
32#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
33#define R0_SC_MPLL_OFF (1U << 18)
34#define R0_SC_SHU_RESTORE (1U << 19)
35#define R0_SC_CKSQ0_OFF (1U << 20)
36#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
37#define R0_SC_DR_SHU_EN (1U << 22)
38#define R0_SC_DPHY_PRECAL_UP (1U << 23)
39#define R0_SC_MPLL_S_OFF (1U << 24)
40#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
41#define R0_SC_PHYPLL_SHU_EN (1U << 26)
42#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
43#define R0_SC_PHYPLL_MODE_SW (1U << 28)
44#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
45#define R0_SC_DR0_SHU_LEVEL (1U << 30)
46#define R0_SC_DR1_SHU_LEVEL (1U << 31)
47/* --- R7 Define --- */
48#define R7_PWRAP_SLEEP_REQ (1U << 0)
49#define R7_EMI_CLK_OFF_REQ_PCM (1U << 1)
50#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
51#define R7_SPM_CK_UPDATE (1U << 3)
52#define R7_SPM_CK_SEL0 (1U << 4)
53#define R7_SPM_CK_SEL1 (1U << 5)
54#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
55#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
56#define R7_SC_26M_CK_SEL (1U << 8)
57#define R7_PCM_TIMER_SET (1U << 9)
58#define R7_PCM_TIMER_CLR (1U << 10)
59#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
60#define R7_CSYSPWRUPACK (1U << 12)
61#define R7_PCM_IM_SLP_EN (1U << 13)
62#define R7_SRCCLKENO0 (1U << 14)
63#define R7_FORCE_DDR_EN_WAKE (1U << 15)
64#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
65#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
66#define R7_SC_AXI_DCM_DIS (1U << 18)
67#define R7_SC_FHC_PAUSE_MEM (1U << 19)
68#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
69#define R7_SRCCLKENO1 (1U << 21)
70#define R7_PCM_WDT_KICK_P (1U << 22)
71#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
72#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
73#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
74#define R7_PMIC_IRQ_REQ_EN (1U << 26)
75#define R7_FORCE_F26M_WAKE (1U << 27)
76#define R7_FORCE_APSRC_WAKE (1U << 28)
77#define R7_FORCE_INFRA_WAKE (1U << 29)
78#define R7_FORCE_VRF18_WAKE (1U << 30)
79#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
80/* --- R12 Define --- */
81#define R12_PCM_TIMER (1U << 0)
82#define R12_TWAM_IRQ_B (1U << 1)
83#define R12_KP_IRQ_B (1U << 2)
84#define R12_APWDT_EVENT_B (1U << 3)
85#define R12_APXGPT1_EVENT_B (1U << 4)
86#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
87#define R12_EINT_EVENT_B (1U << 6)
88#define R12_CONN_WDT_IRQ_B (1U << 7)
89#define R12_CCIF0_EVENT_B (1U << 8)
90#define R12_LOWBATTERY_IRQ_B (1U << 9)
91#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
92#define R12_SCP2SPM_WAKEUP_B (1U << 11)
93#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
94#define R12_PCM_WDT_WAKEUP_B (1U << 13)
95#define R12_USBX_CDSC_B (1U << 14)
96#define R12_USBX_POWERDWN_B (1U << 15)
97#define R12_SYS_TIMER_EVENT_B (1U << 16)
98#define R12_EINT_EVENT_SECURE_B (1U << 17)
99#define R12_CCIF1_EVENT_B (1U << 18)
100#define R12_UART0_IRQ_B (1U << 19)
101#define R12_AFE_IRQ_MCU_B (1U << 20)
102#define R12_THERM_CTRL_EVENT_B (1U << 21)
103#define R12_SYS_CIRQ_IRQ_B (1U << 22)
104#define R12_MD2AP_PEER_EVENT_B (1U << 23)
105#define R12_CSYSPWREQ_B (1U << 24)
106#define R12_NNA_WAKEUP (1U << 25)
107#define R12_CLDMA_EVENT_B (1U << 26)
108#define R12_SEJ_EVENT_B (1U << 27)
109#define R12_REG_CPU_WAKEUP (1U << 28)
110#define R12_CPU_IRQOUT (1U << 29)
111#define R12_CPU_WFI (1U << 30)
112#define R12_MCUSYS_IDLE (1U << 31)
113/* --- R12ext Define --- */
114#define R12EXT_26M_WAKE (1U << 0)
115#define R12EXT_26M_SLEEP (1U << 1)
116#define R12EXT_INFRA_WAKE (1U << 2)
117#define R12EXT_INFRA_SLEEP (1U << 3)
118#define R12EXT_APSRC_WAKE (1U << 4)
119#define R12EXT_APSRC_SLEEP (1U << 5)
120#define R12EXT_VRF18_WAKE (1U << 6)
121#define R12EXT_VRF18_SLEEP (1U << 7)
122#define R12EXT_DVFS_WAKE (1U << 8)
123#define R12EXT_DDREN_WAKE (1U << 9)
124#define R12EXT_DDREN_SLEEP (1U << 10)
125#define R12EXT_MCU_PM_WFI (1U << 11)
126#define R12EXT_SSPM_IDLE (1U << 12)
127#define R12EXT_CONN_SRCCLKENB (1U << 13)
128#define R12EXT_DRAMC_MD32_WFI_MERGE (1U << 14)
129#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
130#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
131#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
132#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
133#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
134#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
135#define R12EXT_BIT21 (1U << 21)
136#define R12EXT_BIT22 (1U << 22)
137#define R12EXT_BIT23 (1U << 23)
138#define R12EXT_BIT24 (1U << 24)
139#define R12EXT_BIT25 (1U << 25)
140#define R12EXT_BIT26 (1U << 26)
141#define R12EXT_BIT27 (1U << 27)
142#define R12EXT_BIT28 (1U << 28)
143#define R12EXT_BIT29 (1U << 29)
144#define R12EXT_BIT30 (1U << 30)
145#define R12EXT_BIT31 (1U << 31)
146/* --- R13 Define --- */
147#define R13_SRCCLKENI0 (1U << 0)
148#define R13_SRCCLKENI1 (1U << 1)
149#define R13_MD_0_SRCCLKENA (1U << 2)
150#define R13_MD_0_APSRC_REQ (1U << 3)
151#define R13_CONN_DDREN (1U << 4)
152#define R13_MD_1_SRCCLKENA (1U << 5)
153#define R13_SSPM_SRCCLKENA (1U << 6)
154#define R13_SSPM_APSRC_REQ (1U << 7)
155#define R13_MD_1_STATE (1U << 8)
156#define R13_RC_SRCCLKENO_ACK (1U << 9)
157#define R13_MM_STATE (1U << 10)
158#define R13_SSPM_STATE (1U << 11)
159#define R13_MD_0_DDREN (1U << 12)
160#define R13_CONN_STATE (1U << 13)
161#define R13_CONN_SRCCLKENA (1U << 14)
162#define R13_CONN_APSRC_REQ (1U << 15)
163#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
164#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
165#define R13_SCP_STATE (1U << 18)
166#define R13_CSYSPWRUPREQ (1U << 19)
167#define R13_PWRAP_SLEEP_ACK (1U << 20)
168#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
169#define R13_AUDIO_DSP_STATE (1U << 22)
170#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
171#define R13_CONN_SRCCLKENB (1U << 24)
172#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
173#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
174#define R13_DVFS_STATE (1U << 27)
175#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
176#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
177#define R13_MD_0_VRF18_REQ (1U << 30)
178#define R13_DDR_EN_STATE (1U << 31)
179
180#endif /* PCM_DEF_H */