| jason-ch chen | a07e3ea | 2021-11-16 10:18:46 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(C)2022, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MT_SPM_VCOREFS_H |
| 8 | #define MT_SPM_VCOREFS_H |
| 9 | |
| 10 | uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4); |
| 11 | |
| 12 | enum vcorefs_smc_cmd { |
| 13 | VCOREFS_SMC_CMD_0 = 0U, |
| 14 | VCOREFS_SMC_CMD_1 = 1U, |
| 15 | VCOREFS_SMC_CMD_2 = 2U, |
| 16 | VCOREFS_SMC_CMD_3 = 3U, |
| 17 | VCOREFS_SMC_CMD_4 = 4U, |
| 18 | /* check spmfw status */ |
| 19 | VCOREFS_SMC_CMD_5 = 5U, |
| 20 | |
| 21 | /* get spmfw type */ |
| 22 | VCOREFS_SMC_CMD_6 = 6U, |
| 23 | |
| 24 | /* get spm reg status */ |
| 25 | VCOREFS_SMC_CMD_7 = 7U, |
| 26 | |
| 27 | NUM_VCOREFS_SMC_CMD = 8U, |
| 28 | }; |
| 29 | |
| 30 | enum vcorefs_smc_cmd_new { |
| 31 | VCOREFS_SMC_CMD_INIT = 0U, |
| 32 | VCOREFS_SMC_CMD_KICK = 1U, |
| 33 | VCOREFS_SMC_CMD_OPP_TYPE = 2U, |
| 34 | VCOREFS_SMC_CMD_FW_TYPE = 3U, |
| 35 | VCOREFS_SMC_CMD_GET_UV = 4U, |
| 36 | VCOREFS_SMC_CMD_GET_FREQ = 5U, |
| 37 | VCOREFS_SMC_CMD_GET_NUM_V = 6U, |
| 38 | VCOREFS_SMC_CMD_GET_NUM_F = 7U, |
| 39 | VCOREFS_SMC_CMD_FB_ACTION = 8U, |
| 40 | /*chip specific setting */ |
| 41 | VCOREFS_SMC_CMD_SET_FREQ = 16U, |
| 42 | VCOREFS_SMC_CMD_SET_EFUSE = 17U, |
| 43 | VCOREFS_SMC_CMD_GET_EFUSE = 18U, |
| 44 | VCOREFS_SMC_CMD_DVFS_HOPPING = 19U, |
| 45 | VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20U, |
| 46 | }; |
| 47 | |
| 48 | enum dvfsrc_channel { |
| 49 | DVFSRC_CHANNEL_1 = 1U, |
| 50 | DVFSRC_CHANNEL_2 = 2U, |
| 51 | DVFSRC_CHANNEL_3 = 3U, |
| 52 | DVFSRC_CHANNEL_4 = 4U, |
| 53 | NUM_DVFSRC_CHANNEL = 5U, |
| 54 | }; |
| 55 | |
| 56 | struct reg_config { |
| 57 | uint32_t offset; |
| 58 | uint32_t val; |
| 59 | }; |
| 60 | |
| 61 | #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) |
| 62 | #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4) |
| 63 | #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8) |
| 64 | #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC) |
| 65 | #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10) |
| 66 | #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) |
| 67 | #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18) |
| 68 | #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C) |
| 69 | #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20) |
| 70 | #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24) |
| 71 | #define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28) |
| 72 | #define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C) |
| 73 | #define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30) |
| 74 | #define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34) |
| 75 | #define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38) |
| 76 | #define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C) |
| 77 | #define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40) |
| 78 | #define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44) |
| 79 | #define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48) |
| 80 | #define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C) |
| 81 | #define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50) |
| 82 | #define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54) |
| 83 | #define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58) |
| 84 | #define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C) |
| 85 | #define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60) |
| 86 | #define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64) |
| 87 | #define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68) |
| 88 | #define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C) |
| 89 | #define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70) |
| 90 | #define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74) |
| 91 | #define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78) |
| 92 | #define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C) |
| 93 | #define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80) |
| 94 | #define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84) |
| 95 | #define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88) |
| 96 | #define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C) |
| 97 | #define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90) |
| 98 | #define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94) |
| 99 | #define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98) |
| 100 | #define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C) |
| 101 | #define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0) |
| 102 | #define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4) |
| 103 | #define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8) |
| 104 | #define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC) |
| 105 | #define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0) |
| 106 | #define DVFSRC_INT (DVFSRC_BASE + 0xC4) |
| 107 | #define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8) |
| 108 | #define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC) |
| 109 | #define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0) |
| 110 | #define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4) |
| 111 | #define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8) |
| 112 | #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC) |
| 113 | #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4) |
| 114 | #define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0) |
| 115 | #define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4) |
| 116 | #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) |
| 117 | #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100) |
| 118 | #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104) |
| 119 | #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108) |
| 120 | #define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C) |
| 121 | #define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110) |
| 122 | #define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114) |
| 123 | #define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118) |
| 124 | #define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C) |
| 125 | #define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200) |
| 126 | #define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204) |
| 127 | #define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208) |
| 128 | #define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C) |
| 129 | #define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210) |
| 130 | #define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214) |
| 131 | #define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218) |
| 132 | #define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C) |
| 133 | #define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220) |
| 134 | #define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224) |
| 135 | #define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228) |
| 136 | #define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C) |
| 137 | #define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230) |
| 138 | #define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234) |
| 139 | #define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238) |
| 140 | #define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C) |
| 141 | #define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240) |
| 142 | #define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244) |
| 143 | #define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248) |
| 144 | #define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C) |
| 145 | #define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250) |
| 146 | #define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254) |
| 147 | #define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258) |
| 148 | #define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C) |
| 149 | #define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260) |
| 150 | #define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264) |
| 151 | #define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268) |
| 152 | #define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C) |
| 153 | #define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270) |
| 154 | #define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274) |
| 155 | #define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278) |
| 156 | #define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280) |
| 157 | #define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284) |
| 158 | #define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290) |
| 159 | #define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294) |
| 160 | #define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304) |
| 161 | #define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308) |
| 162 | #define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C) |
| 163 | #define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310) |
| 164 | #define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314) |
| 165 | #define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318) |
| 166 | #define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500) |
| 167 | #define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504) |
| 168 | #define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508) |
| 169 | #define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C) |
| 170 | #define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510) |
| 171 | #define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514) |
| 172 | #define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518) |
| 173 | #define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C) |
| 174 | #define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520) |
| 175 | #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524) |
| 176 | #define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528) |
| 177 | #define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C) |
| 178 | #define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530) |
| 179 | #define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534) |
| 180 | #define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538) |
| 181 | #define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C) |
| 182 | #define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540) |
| 183 | #define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544) |
| 184 | #define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548) |
| 185 | #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600) |
| 186 | #define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604) |
| 187 | #define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608) |
| 188 | #define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C) |
| 189 | #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) |
| 190 | #define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614) |
| 191 | #define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630) |
| 192 | #define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700) |
| 193 | #define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704) |
| 194 | #define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708) |
| 195 | #define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C) |
| 196 | #define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710) |
| 197 | #define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800) |
| 198 | #define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804) |
| 199 | #define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808) |
| 200 | #define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C) |
| 201 | #define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810) |
| 202 | #define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814) |
| 203 | #define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00) |
| 204 | #define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04) |
| 205 | #define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08) |
| 206 | #define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C) |
| 207 | #define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10) |
| 208 | #define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14) |
| 209 | #define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18) |
| 210 | #define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C) |
| 211 | #define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20) |
| 212 | #define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24) |
| 213 | #define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28) |
| 214 | #define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C) |
| 215 | #define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30) |
| 216 | #define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34) |
| 217 | #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38) |
| 218 | #define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C) |
| 219 | #define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40) |
| 220 | #define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44) |
| 221 | #define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48) |
| 222 | #define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C) |
| 223 | #define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50) |
| 224 | #define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54) |
| 225 | #define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58) |
| 226 | #define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C) |
| 227 | #define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60) |
| 228 | #define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64) |
| 229 | #define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68) |
| 230 | #define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C) |
| 231 | #define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70) |
| 232 | #define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74) |
| 233 | #define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78) |
| 234 | #define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C) |
| 235 | #define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80) |
| 236 | #define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84) |
| 237 | #define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88) |
| 238 | #define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C) |
| 239 | #define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90) |
| 240 | #define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94) |
| 241 | #define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98) |
| 242 | #define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C) |
| 243 | #define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0) |
| 244 | #define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4) |
| 245 | #define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8) |
| 246 | #define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC) |
| 247 | #define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0) |
| 248 | #define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4) |
| 249 | #define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8) |
| 250 | #define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC) |
| 251 | #define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0) |
| 252 | #define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4) |
| 253 | #define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8) |
| 254 | #define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC) |
| 255 | #define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0) |
| 256 | #define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4) |
| 257 | #define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8) |
| 258 | #define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC) |
| 259 | #define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0) |
| 260 | #define DVFSRC_LAST (DVFSRC_BASE + 0xAE4) |
| 261 | #define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8) |
| 262 | #define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC) |
| 263 | #define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0) |
| 264 | #define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4) |
| 265 | #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8) |
| 266 | #define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC) |
| 267 | #define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00) |
| 268 | #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04) |
| 269 | #define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08) |
| 270 | #define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C) |
| 271 | #define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0) |
| 272 | #define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4) |
| 273 | #define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8) |
| 274 | #define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC) |
| 275 | #define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00) |
| 276 | #define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04) |
| 277 | #define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08) |
| 278 | #define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C) |
| 279 | #define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0) |
| 280 | #define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4) |
| 281 | #define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8) |
| 282 | #define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC) |
| 283 | #define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00) |
| 284 | #define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04) |
| 285 | #define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08) |
| 286 | #define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C) |
| 287 | #define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10) |
| 288 | #define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14) |
| 289 | #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18) |
| 290 | #define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C) |
| 291 | #define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20) |
| 292 | #define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24) |
| 293 | #define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28) |
| 294 | #define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C) |
| 295 | #define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30) |
| 296 | #define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34) |
| 297 | #define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38) |
| 298 | #define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C) |
| 299 | #define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40) |
| 300 | #define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44) |
| 301 | #define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48) |
| 302 | #define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C) |
| 303 | #define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50) |
| 304 | #define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54) |
| 305 | #define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58) |
| 306 | #define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C) |
| 307 | #define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60) |
| 308 | #define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64) |
| 309 | #define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68) |
| 310 | #define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C) |
| 311 | #define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70) |
| 312 | #define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74) |
| 313 | |
| 314 | #define VCORE_VB_EFUSE (0x11C105E8) |
| 315 | |
| 316 | #endif /* MT_SPM_VCOREFS_H */ |