blob: 219b8d3eb46d18eaebf9b484c848df39f48882db [file] [log] [blame]
jason-ch chenfa82b9b2021-11-16 09:48:20 +08001/*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/****************************************************************
8 * Auto generated by DE, please DO NOT modify this file directly.
9 *****************************************************************/
10#ifndef MT_SPM_PMIC_WRAP_H
11#define MT_SPM_PMIC_WRAP_H
12
13enum pmic_wrap_phase_id {
14 PMIC_WRAP_PHASE_ALLINONE = 0U,
15 NR_PMIC_WRAP_PHASE = 1U,
16};
17
18/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
19enum {
20 CMD_0 = 0U, /* 0x0 */
21 CMD_1 = 1U, /* 0x1 */
22 CMD_2 = 2U, /* 0x2 */
23 CMD_3 = 3U, /* 0x3 */
24 CMD_4 = 4U, /* 0x4 */
25 CMD_5 = 5U, /* 0x5 */
26 CMD_6 = 6U, /* 0x6 */
27 CMD_7 = 7U, /* 0x7 */
28 CMD_8 = 8U, /* 0x8 */
29 NR_IDX_ALL = 9U,
30};
31
32/* APIs */
33extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
34extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
35 uint32_t idx, uint32_t cmd_wdata);
36extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
37 uint32_t idx);
38
39#endif /* MT_SPM_PMIC_WRAP_H */