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git01.mediatek.com / filogic / atf / e1598e545fa758ca4779c367dd3df2720f1f9c4d / . / plat / mediatek / mt8186 / drivers / spm / mt_spm_internal.c
blob: f228961dca28f2288e782a93a75bca514d4c374a [file] [log] [blame]
jason-ch chenfa82b9b2021-11-16 09:48:20 +0800[diff] [blame]1/*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stddef.h>
9#include <common/debug.h>
10#include <drivers/delay_timer.h>
11#include <lib/mmio.h>
12#include <mt_spm.h>
13#include <mt_spm_internal.h>
14#include <mt_spm_reg.h>
15#include <mt_spm_resource_req.h>
16#include <plat_pm.h>
17#include <platform_def.h>
18
19/* Define and Declare */
20#define ROOT_CORE_ADDR_OFFSET (0x20000000)
21#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK (0xefffffff)
22#define SPM_INIT_DONE_US (20)
23
24static unsigned int mt_spm_bblpm_cnt;
25
26const char *wakeup_src_str[32] = {
27 [0] = "R12_PCM_TIMER",
28 [1] = "R12_RESERVED_DEBUG_B",
29 [2] = "R12_KP_IRQ_B",
30 [3] = "R12_APWDT_EVENT_B",
31 [4] = "R12_APXGPT1_EVENT_B",
32 [5] = "R12_CONN2AP_SPM_WAKEUP_B",
33 [6] = "R12_EINT_EVENT_B",
34 [7] = "R12_CONN_WDT_IRQ_B",
35 [8] = "R12_CCIF0_EVENT_B",
36 [9] = "R12_LOWBATTERY_IRQ_B",
37 [10] = "R12_SC_SSPM2SPM_WAKEUP_B",
38 [11] = "R12_SC_SCP2SPM_WAKEUP_B",
39 [12] = "R12_SC_ADSP2SPM_WAKEUP_B",
40 [13] = "R12_PCM_WDT_WAKEUP_B",
41 [14] = "R12_USB_CDSC_B",
42 [15] = "R12_USB_POWERDWN_B",
43 [16] = "R12_SYS_TIMER_EVENT_B",
44 [17] = "R12_EINT_EVENT_SECURE_B",
45 [18] = "R12_CCIF1_EVENT_B",
46 [19] = "R12_UART0_IRQ_B",
47 [20] = "R12_AFE_IRQ_MCU_B",
48 [21] = "R12_THERM_CTRL_EVENT_B",
49 [22] = "R12_SYS_CIRQ_IRQ_B",
50 [23] = "R12_MD2AP_PEER_EVENT_B",
51 [24] = "R12_CSYSPWREQ_B",
52 [25] = "R12_MD1_WDT_B",
53 [26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
54 [27] = "R12_SEJ_EVENT_B",
55 [28] = "R12_SPM_CPU_WAKEUPEVENT_B",
56 [29] = "R12_APUSYS",
57 [30] = "R12_PCIE_BRIDGE_IRQ",
58 [31] = "R12_PCIE_IRQ",
59};
60
61/* Function and API */
62wake_reason_t __spm_output_wake_reason(int state_id, const struct wake_status *wakesta)
63{
64 uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
65 wake_reason_t wr = WR_UNKNOWN;
66
67 if (wakesta != NULL) {
68 if (wakesta->abort != 0U) {
69 ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
70 wakesta->abort, wakesta->timer_out);
71 } else {
72 for (i = 0U; i < 32U; i++) {
73 if ((wakesta->r12 & BIT(i)) != 0U) {
74 INFO("wake up by %s, timer_out = %u\n",
75 wakeup_src_str[i], wakesta->timer_out);
76 wr = WR_WAKE_SRC;
77 break;
78 }
79 }
80 }
81
82 INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
83 wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
84 wakesta->debug_flag1);
85 INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
86 wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
87 wakesta->md32pcm_event_sta, wakesta->idle_sta,
88 wakesta->cg_check_sta);
89 INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
90 wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
91 wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
92 INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
93 wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
94 INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
95 wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
96 INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
97 wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
98 wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
99 INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
100 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
101 mmio_read_32(SYS_TIMER_VALUE_H));
102
103 if (wakesta->timer_out != 0U) {
104 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
105 spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
106 INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
107 }
108 }
109
110 return wr;
111}
112
113void __spm_set_cpu_status(unsigned int cpu)
114{
115 uint32_t root_core_addr;
116
117 if (cpu < 8U) {
118 mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
119
120 root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
121 root_core_addr += ROOT_CORE_ADDR_OFFSET;
122 mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
123
124 /* Notify SSPM that preferred cpu wakeup */
125 mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
126 } else {
127 ERROR("%s: error cpu number %d\n", __func__, cpu);
128 }
129}
130
131void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
132 unsigned int resource_usage)
133{
134 uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
135 1 : pwrctrl->reg_spm_apsrc_req;
136 uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
137 1 : pwrctrl->reg_spm_ddren_req;
138 uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
139 1 : pwrctrl->reg_spm_vrf18_req;
140 uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
141 1 : pwrctrl->reg_spm_infra_req;
142 uint8_t f26m_req = ((resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
143 1 : pwrctrl->reg_spm_f26m_req;
144
145 /*
146 * if SPM_FLAG_SSPM_INFRA_SLEEP_MODE set,
147 * clear sspm_srclkena_mask_b and sspm_infra_mask_b
148 */
149 uint8_t reg_sspm_srcclkena_mask_b =
150 (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
151 ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;
152
153 uint8_t reg_sspm_infra_req_mask_b =
154 (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
155 ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;
156
157 /* SPM_SRC_REQ */
158 mmio_write_32(SPM_SRC_REQ,
159 ((apsrc_req & 0x1) << 0) |
160 ((f26m_req & 0x1) << 1) |
161 ((infra_req & 0x1) << 3) |
162 ((vrf18_req & 0x1) << 4) |
163 ((ddr_en_req & 0x1) << 7) |
164 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
165 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
166 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
167 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
168 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
169
170 /* SPM_SRC_MASK */
171 mmio_write_32(SPM_SRC_MASK,
172 ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
173 ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
174 ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
175 ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
176 ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
177 ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
178 ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
179 ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
180 ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
181 ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
182 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
183 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
184 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
185 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
186 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
187 ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
188 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
189 ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
190 ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
191 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
192 ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
193 ((reg_sspm_srcclkena_mask_b & 0x1) << 27) |
194 ((reg_sspm_infra_req_mask_b & 0x1) << 28) |
195 ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
196 ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
197 ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
198}
199
200void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
201{
202 /* Auto-gen Start */
203
204 /* SPM_AP_STANDBY_CON */
205 mmio_write_32(SPM_AP_STANDBY_CON,
206 ((pwrctrl->reg_wfi_op & 0x1) << 0) |
207 ((pwrctrl->reg_wfi_type & 0x1) << 1) |
208 ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
209 ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
210 ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
211 ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
212 ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
213 ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
214
215 /* SPM_SRC6_MASK */
216 mmio_write_32(SPM_SRC6_MASK,
217 ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
218 ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
219
220 /* SPM_SRC_REQ */
221 mmio_write_32(SPM_SRC_REQ,
222 ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
223 ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
224 ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
225 ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
226 ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
227 ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
228 ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
229 ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
230 ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
231 ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
232
233 /* SPM_SRC_MASK */
234 mmio_write_32(SPM_SRC_MASK,
235 ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
236 ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
237 ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
238 ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
239 ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
240 ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
241 ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
242 ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
243 ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
244 ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
245 ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
246 ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
247 ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
248 ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
249 ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
250 ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
251 ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
252 ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
253 ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
254 ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
255 ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
256 ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
257 ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
258 ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
259 ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
260 ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
261
262 /* SPM_SRC2_MASK */
263 mmio_write_32(SPM_SRC2_MASK,
264 ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
265 ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
266 ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
267 ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
268 ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
269 ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
270 ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
271 ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
272 ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
273 ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
274 ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
275 ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
276 ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
277 ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
278 ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
279 ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
280 ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
281 ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
282 ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
283 ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
284 ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
285 ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
286 ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
287 ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
288 ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
289 ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
290 ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
291 ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
292 ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
293 ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
294 ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
295 ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
296
297 /* SPM_SRC3_MASK */
298 mmio_write_32(SPM_SRC3_MASK,
299 ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
300 ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
301 ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
302 ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
303 ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
304 ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
305 ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
306 ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
307 ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
308 ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
309 ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
310 ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
311 ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
312 ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
313 ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
314 ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
315 ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
316 ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
317 ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
318 ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
319 ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
320 ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
321 ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
322 ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
323 ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
324 ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
325
326 /* SPM_SRC4_MASK */
327 mmio_write_32(SPM_SRC4_MASK,
328 ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
329 ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
330 ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
331 ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
332 ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
333 ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
334 ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
335 ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
336 ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
337 ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
338
339 /* SPM_SRC5_MASK */
340 mmio_write_32(SPM_SRC5_MASK,
341 ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
342 ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
343 ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
344 ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
345 ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
346 ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
347 ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
348 ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
349 ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
350 ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
351 ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
352 ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
353
354 /* SPM_WAKEUP_EVENT_MASK */
355 mmio_write_32(SPM_WAKEUP_EVENT_MASK,
356 ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
357
358 /* SPM_WAKEUP_EVENT_EXT_MASK */
359 mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
360 ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
361
362 /* SPM_SRC7_MASK */
363 mmio_write_32(SPM_SRC7_MASK,
364 ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
365 ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
366 ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
367 ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
368 ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
369 ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
370 ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
371 ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
372 ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
373 ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
374 /* Auto-gen End */
375}
376
377void __spm_disable_pcm_timer(void)
378{
379 mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
380}
381
382
383void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
384{
385 uint32_t val, mask;
386
387 /* toggle event counter clear */
388 mmio_setbits_32(PCM_CON1,
389 SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
390
391 /* toggle for reset SYS TIMER start point */
392 mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
393
394 if (pwrctrl->timer_val_cust == 0U) {
395 val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);
396 } else {
397 val = pwrctrl->timer_val_cust;
398 }
399
400 mmio_write_32(PCM_TIMER_VAL, val);
401 mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB));
402
403 /* unmask AP wakeup source */
404 if (pwrctrl->wake_src_cust == 0U) {
405 mask = pwrctrl->wake_src;
406 } else {
407 mask = pwrctrl->wake_src_cust;
408 }
409
410 if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {
411 mask &= ~R12_CSYSPWREQ_B;
412 }
413
414 mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
415
416 /* unmask SPM ISR (keep TWAM setting) */
417 mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
418
419 /* toggle event counter clear */
420 mmio_clrsetbits_32(PCM_CON1, REG_SPM_EVENT_COUNTER_CLR_LSB,
421 SPM_REGWR_CFG_KEY);
422 /* toggle for reset SYS TIMER start point */
423 mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
424}
425
426void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
427{
428 /* set PCM flags and data */
429 if (pwrctrl->pcm_flags_cust_clr != 0U) {
430 pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
431 }
432
433 if (pwrctrl->pcm_flags_cust_set != 0U) {
434 pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
435 }
436
437 if (pwrctrl->pcm_flags1_cust_clr != 0U) {
438 pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
439 }
440
441 if (pwrctrl->pcm_flags1_cust_set != 0U) {
442 pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
443 }
444
445 mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
446
447 mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
448
449 mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
450
451 mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
452}
453
454void __spm_get_wakeup_status(struct wake_status *wakesta,
455 unsigned int ext_status)
456{
457 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
458 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
459 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
460 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
461 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
462 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
463 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
464 wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
465
466 wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
467 wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
468
469 if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
470 wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
471 SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
472 mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
473 }
474
475 wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
476 wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
477
478 /* record below spm info for debug */
479 wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
480 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
481 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
482 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
483 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
484 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
485 wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
486
487 /* backup of SPM_WAKEUP_MISC */
488 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
489
490 /* get sleep time, backup of PCM_TIMER_OUT */
491 wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
492
493 /* get other SYS and co-clock status */
494 wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
495 wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
496 wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
497 wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
498 wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
499 wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
500 wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
501
502 /* get HW CG check status */
503 wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
504
505 /* get debug flag for PCM execution check */
506 wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
507 wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
508
509 /* get backup SW flag status */
510 wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
511 wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
512
513 wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
514 wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
515 wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
516 wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
517 wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
518
519 /* get ISR status */
520 wakesta->isr = mmio_read_32(SPM_IRQ_STA);
521
522 /* get SW flag status */
523 wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
524 wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
525
526 /* get CLK SETTLE */
527 wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
528
529 /* check abort */
530 wakesta->abort = ((wakesta->debug_flag & DEBUG_ABORT_MASK) |
531 (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1));
532}
533
534void __spm_clean_after_wakeup(void)
535{
536 mmio_write_32(SPM_BK_WAKE_EVENT,
537 (mmio_read_32(SPM_WAKEUP_STA) |
538 mmio_read_32(SPM_BK_WAKE_EVENT)));
539 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
540
541 /*
542 * clean wakeup event raw status (for edge trigger event)
543 * bit[28] for cpu wake up event
544 */
545 mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
546
547 /* clean ISR status (except TWAM) */
548 mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
549 mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
550 mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
551}
552
553void __spm_set_pcm_wdt(int en)
554{
555 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
556 SPM_REGWR_CFG_KEY);
557
558 if (en == 1) {
559 mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
560 SPM_REGWR_CFG_KEY);
561
562 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
563 mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
564 }
565
566 mmio_write_32(PCM_WDT_VAL,
567 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
568 mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
569 }
570}
571
572void __spm_send_cpu_wakeup_event(void)
573{
574 /* SPM will clear SPM_CPU_WAKEUP_EVENT */
575 mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
576}
577
578void __spm_ext_int_wakeup_req_clr(void)
579{
580 unsigned int reg = mmio_read_32(SPM_MD32_IRQ) & (~(0x1U << 0));
581
582 mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
583
584 /* Clear spm2mcupm wakeup interrupt status */
585 mmio_write_32(SPM_MD32_IRQ, reg);
586}
587
588void __spm_xo_soc_bblpm(int en)
589{
590 if (en == 1) {
591 mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
592 RC_SW_SRCCLKEN_FPM, RC_SW_SRCCLKEN_RC);
593 assert(mt_spm_bblpm_cnt == 0);
594 mt_spm_bblpm_cnt += 1;
595 } else {
596 mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
597 RC_SW_SRCCLKEN_RC, RC_SW_SRCCLKEN_FPM);
598 mt_spm_bblpm_cnt -= 1;
599 }
600}
601
602void __spm_hw_s1_state_monitor(int en, unsigned int *status)
603{
604 unsigned int reg = mmio_read_32(SPM_ACK_CHK_CON_3);
605
606 if (en == 1) {
607 reg = mmio_read_32(SPM_ACK_CHK_CON_3);
608 reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
609 mmio_write_32(SPM_ACK_CHK_CON_3, reg);
610 reg |= SPM_ACK_CHK_3_CON_EN;
611 mmio_write_32(SPM_ACK_CHK_CON_3, reg);
612 } else {
613 if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
614 (status != NULL)) {
615 *status |= SPM_INTERNAL_STATUS_HW_S1;
616 }
617
618 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
619 SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
620 SPM_ACK_CHK_3_CON_CLR_ALL);
621 }
622}
623