blob: dfacba961704e82628537f2028901799c3efc82b [file] [log] [blame]
jason-ch chenfa82b9b2021-11-16 09:48:20 +08001/*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef MT_SPM_RC_INTERNAL_H
8#define MT_SPM_RC_INTERNAL_H
9
10#include <stdbool.h>
11
12#define SPM_SRAM_SLEEP_DEFAULT_FLAG (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
13
14#define SPM_FLAG_SRAM_SLEEP_CTRL \
15 (SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \
16 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
17 SPM_FLAG_DISABLE_SYSRAM_SLEEP | \
18 SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP | \
19 SPM_FLAG_DISABLE_SRAM_EVENT)
20
21/* cpu buck/ldo constraint function */
22bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
23unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
24int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
25int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
26
27/* spm resource dram constraint function */
28bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
29int spm_update_rc_dram(int state_id, int type, const void *val);
30unsigned int spm_allow_rc_dram(int state_id);
31int spm_run_rc_dram(unsigned int cpu, int state_id);
32int spm_reset_rc_dram(unsigned int cpu, int state_id);
33
34/* spm resource syspll constraint function */
35bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
36int spm_update_rc_syspll(int state_id, int type, const void *val);
37unsigned int spm_allow_rc_syspll(int state_id);
38int spm_run_rc_syspll(unsigned int cpu, int state_id);
39int spm_reset_rc_syspll(unsigned int cpu, int state_id);
40
41/* spm resource bus26m constraint function */
42bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
43int spm_update_rc_bus26m(int state_id, int type, const void *val);
44unsigned int spm_allow_rc_bus26m(int state_id);
45int spm_run_rc_bus26m(unsigned int cpu, int state_id);
46int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
47
48#endif /* MT_SPM_RC_INTERNAL_H */