Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame^] | 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include "../qos_common.h" |
| 12 | #include "qos_init_m3_v10.h" |
| 13 | |
| 14 | #define RCAR_QOS_VERSION "rev.0.19" |
| 15 | |
| 16 | #define RCAR_QOS_NONE (3U) |
| 17 | #define RCAR_QOS_TYPE_DEFAULT (0U) |
| 18 | |
| 19 | #define RCAR_DRAM_SPLIT_LINEAR (0U) |
| 20 | #define RCAR_DRAM_SPLIT_4CH (1U) |
| 21 | #define RCAR_DRAM_SPLIT_2CH (2U) |
| 22 | #define RCAR_DRAM_SPLIT_AUTO (3U) |
| 23 | |
| 24 | #define RST_BASE (0xE6160000U) |
| 25 | #define RST_MODEMR (RST_BASE + 0x0060U) |
| 26 | |
| 27 | #define DBSC_BASE (0xE6790000U) |
| 28 | #define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) |
| 29 | #define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) |
| 30 | #define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) |
| 31 | #define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) |
| 32 | #define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) |
| 33 | #define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) |
| 34 | #define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) |
| 35 | #define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) |
| 36 | #define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) |
| 37 | #define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) |
| 38 | #define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) |
| 39 | #define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) |
| 40 | #define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) |
| 41 | #define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) |
| 42 | #define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) |
| 43 | #define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) |
| 44 | #define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) |
| 45 | #define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) |
| 46 | #define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) |
| 47 | #define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) |
| 48 | #define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) |
| 49 | #define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) |
| 50 | #define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) |
| 51 | #define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) |
| 52 | #define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) |
| 53 | #define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) |
| 54 | #define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) |
| 55 | #define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) |
| 56 | #define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) |
| 57 | #define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) |
| 58 | #define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) |
| 59 | #define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) |
| 60 | #define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) |
| 61 | #define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) |
| 62 | #define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) |
| 63 | #define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) |
| 64 | #define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) |
| 65 | #define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) |
| 66 | #define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) |
| 67 | #define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) |
| 68 | #define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) |
| 69 | #define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) |
| 70 | #define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) |
| 71 | #define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) |
| 72 | #define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) |
| 73 | #define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) |
| 74 | #define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) |
| 75 | #define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) |
| 76 | #define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) |
| 77 | #define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) |
| 78 | #define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) |
| 79 | #define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) |
| 80 | #define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) |
| 81 | #define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) |
| 82 | #define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) |
| 83 | #define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) |
| 84 | #define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) |
| 85 | #define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) |
| 86 | #define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) |
| 87 | #define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) |
| 88 | #define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) |
| 89 | #define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) |
| 90 | #define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) |
| 91 | #define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) |
| 92 | #define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) |
| 93 | #define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) |
| 94 | #define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) |
| 95 | #define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) |
| 96 | #define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) |
| 97 | #define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) |
| 98 | #define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) |
| 99 | #define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) |
| 100 | #define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) |
| 101 | #define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) |
| 102 | |
| 103 | #define AXI_BASE (0xE6784000U) |
| 104 | #define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) |
| 105 | #define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) |
| 106 | #define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) |
| 107 | #define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) |
| 108 | #define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) |
| 109 | #define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) |
| 110 | #define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) |
| 111 | #define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) |
| 112 | #define ADSPLCR0_SWP (0x0CU) |
| 113 | |
| 114 | #define MSTAT_BASE (0xE67E0000U) |
| 115 | #define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) |
| 116 | #define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) |
| 117 | #define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) |
| 118 | #define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) |
| 119 | #define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) |
| 120 | #define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) |
| 121 | #define MSTAT_STATQC (MSTAT_BASE + 0x8008U) |
| 122 | |
| 123 | #define RALLOC_BASE (0xE67F0000U) |
| 124 | #define RALLOC_RAS (RALLOC_BASE + 0x0000U) |
| 125 | #define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) |
| 126 | #define RALLOC_RAEN (RALLOC_BASE + 0x0018U) |
| 127 | #define RALLOC_REGGD (RALLOC_BASE + 0x0020U) |
| 128 | #define RALLOC_DANN (RALLOC_BASE + 0x0030U) |
| 129 | #define RALLOC_DANT (RALLOC_BASE + 0x0038U) |
| 130 | #define RALLOC_EC (RALLOC_BASE + 0x003CU) |
| 131 | #define RALLOC_EMS (RALLOC_BASE + 0x0040U) |
| 132 | #define RALLOC_FSS (RALLOC_BASE + 0x0048U) |
| 133 | #define RALLOC_INSFC (RALLOC_BASE + 0x0050U) |
| 134 | #define RALLOC_BERR (RALLOC_BASE + 0x0054U) |
| 135 | #define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) |
| 136 | |
| 137 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 138 | static const mstat_slot_t mstat_fix[] = { |
| 139 | {0x0000U, 0x0000000000000000UL}, |
| 140 | {0x0008U, 0x0000000000000000UL}, |
| 141 | {0x0010U, 0x0000000000000000UL}, |
| 142 | {0x0018U, 0x0000000000000000UL}, |
| 143 | {0x0020U, 0x0000000000000000UL}, |
| 144 | {0x0028U, 0x0000000000000000UL}, |
| 145 | {0x0030U, 0x001004030000FFFFUL}, |
| 146 | {0x0038U, 0x001004030000FFFFUL}, |
| 147 | {0x0040U, 0x001414090000FFFFUL}, |
| 148 | {0x0048U, 0x0000000000000000UL}, |
| 149 | {0x0050U, 0x001410010000FFFFUL}, |
| 150 | {0x0058U, 0x00140C090000FFFFUL}, |
| 151 | {0x0060U, 0x00140C090000FFFFUL}, |
| 152 | {0x0068U, 0x0000000000000000UL}, |
| 153 | {0x0070U, 0x001410010000FFFFUL}, |
| 154 | {0x0078U, 0x001004020000FFFFUL}, |
| 155 | {0x0080U, 0x0000000000000000UL}, |
| 156 | {0x0088U, 0x001414090000FFFFUL}, |
| 157 | {0x0090U, 0x001408060000FFFFUL}, |
| 158 | {0x0098U, 0x0000000000000000UL}, |
| 159 | {0x00A0U, 0x000C08020000FFFFUL}, |
| 160 | {0x00A8U, 0x000C04010000FFFFUL}, |
| 161 | {0x00B0U, 0x000C04010000FFFFUL}, |
| 162 | {0x00B8U, 0x0000000000000000UL}, |
| 163 | {0x00C0U, 0x000C08020000FFFFUL}, |
| 164 | {0x00C8U, 0x000C04010000FFFFUL}, |
| 165 | {0x00D0U, 0x000C04010000FFFFUL}, |
| 166 | {0x00D8U, 0x000C04030000FFFFUL}, |
| 167 | {0x00E0U, 0x000C100F0000FFFFUL}, |
| 168 | {0x00E8U, 0x0000000000000000UL}, |
| 169 | {0x00F0U, 0x001010080000FFFFUL}, |
| 170 | {0x00F8U, 0x0000000000000000UL}, |
| 171 | {0x0100U, 0x0000000000000000UL}, |
| 172 | {0x0108U, 0x0000000000000000UL}, |
| 173 | {0x0110U, 0x001010080000FFFFUL}, |
| 174 | {0x0118U, 0x0000000000000000UL}, |
| 175 | {0x0120U, 0x0000000000000000UL}, |
| 176 | {0x0128U, 0x0000000000000000UL}, |
| 177 | {0x0130U, 0x0000000000000000UL}, |
| 178 | {0x0138U, 0x00100C0A0000FFFFUL}, |
| 179 | {0x0140U, 0x0000000000000000UL}, |
| 180 | {0x0148U, 0x0000000000000000UL}, |
| 181 | {0x0150U, 0x00100C0A0000FFFFUL}, |
| 182 | {0x0158U, 0x0000000000000000UL}, |
| 183 | {0x0160U, 0x00100C0A0000FFFFUL}, |
| 184 | {0x0168U, 0x0000000000000000UL}, |
| 185 | {0x0170U, 0x0000000000000000UL}, |
| 186 | {0x0178U, 0x001008050000FFFFUL}, |
| 187 | {0x0180U, 0x0000000000000000UL}, |
| 188 | {0x0188U, 0x0000000000000000UL}, |
| 189 | {0x0190U, 0x001028280000FFFFUL}, |
| 190 | {0x0198U, 0x0000000000000000UL}, |
| 191 | {0x01A0U, 0x00100C0A0000FFFFUL}, |
| 192 | {0x01A8U, 0x0000000000000000UL}, |
| 193 | {0x01B0U, 0x0000000000000000UL}, |
| 194 | {0x01B8U, 0x0000000000000000UL}, |
| 195 | {0x01C0U, 0x0000000000000000UL}, |
| 196 | {0x01C8U, 0x0000000000000000UL}, |
| 197 | {0x01D0U, 0x0000000000000000UL}, |
| 198 | {0x01D8U, 0x0000000000000000UL}, |
| 199 | {0x01E0U, 0x0000000000000000UL}, |
| 200 | {0x01E8U, 0x0000000000000000UL}, |
| 201 | {0x01F0U, 0x0000000000000000UL}, |
| 202 | {0x01F8U, 0x0000000000000000UL}, |
| 203 | {0x0200U, 0x0000000000000000UL}, |
| 204 | {0x0208U, 0x0000000000000000UL}, |
| 205 | {0x0210U, 0x0000000000000000UL}, |
| 206 | {0x0218U, 0x0000000000000000UL}, |
| 207 | {0x0220U, 0x0000000000000000UL}, |
| 208 | {0x0228U, 0x0000000000000000UL}, |
| 209 | {0x0230U, 0x0000000000000000UL}, |
| 210 | {0x0238U, 0x0000000000000000UL}, |
| 211 | {0x0240U, 0x0000000000000000UL}, |
| 212 | {0x0248U, 0x0000000000000000UL}, |
| 213 | {0x0250U, 0x0000000000000000UL}, |
| 214 | {0x0258U, 0x0000000000000000UL}, |
| 215 | {0x0260U, 0x0000000000000000UL}, |
| 216 | {0x0268U, 0x001408010000FFFFUL}, |
| 217 | {0x0270U, 0x001404010000FFFFUL}, |
| 218 | {0x0278U, 0x0000000000000000UL}, |
| 219 | {0x0280U, 0x0000000000000000UL}, |
| 220 | {0x0288U, 0x0000000000000000UL}, |
| 221 | {0x0290U, 0x001408010000FFFFUL}, |
| 222 | {0x0298U, 0x001404010000FFFFUL}, |
| 223 | {0x02A0U, 0x000C04010000FFFFUL}, |
| 224 | {0x02A8U, 0x000C04010000FFFFUL}, |
| 225 | {0x02B0U, 0x001404010000FFFFUL}, |
| 226 | {0x02B8U, 0x0000000000000000UL}, |
| 227 | {0x02C0U, 0x0000000000000000UL}, |
| 228 | {0x02C8U, 0x0000000000000000UL}, |
| 229 | {0x02D0U, 0x000C04010000FFFFUL}, |
| 230 | {0x02D8U, 0x000C04010000FFFFUL}, |
| 231 | {0x02E0U, 0x001404010000FFFFUL}, |
| 232 | {0x02E8U, 0x0000000000000000UL}, |
| 233 | {0x02F0U, 0x0000000000000000UL}, |
| 234 | {0x02F8U, 0x0000000000000000UL}, |
| 235 | {0x0300U, 0x0000000000000000UL}, |
| 236 | {0x0308U, 0x0000000000000000UL}, |
| 237 | {0x0310U, 0x0000000000000000UL}, |
| 238 | {0x0318U, 0x0000000000000000UL}, |
| 239 | {0x0320U, 0x0000000000000000UL}, |
| 240 | {0x0328U, 0x0000000000000000UL}, |
| 241 | {0x0330U, 0x0000000000000000UL}, |
| 242 | {0x0338U, 0x0000000000000000UL}, |
| 243 | {0x0340U, 0x0000000000000000UL}, |
| 244 | {0x0348U, 0x0000000000000000UL}, |
| 245 | {0x0350U, 0x0000000000000000UL}, |
| 246 | }; |
| 247 | |
| 248 | static const mstat_slot_t mstat_be[] = { |
| 249 | {0x0000U, 0x001200100C89C401UL}, |
| 250 | {0x0008U, 0x001200100C89C401UL}, |
| 251 | {0x0010U, 0x001200100C89C401UL}, |
| 252 | {0x0018U, 0x001200100C89C401UL}, |
| 253 | {0x0020U, 0x0000000000000000UL}, |
| 254 | {0x0028U, 0x001100100C803401UL}, |
| 255 | {0x0030U, 0x0000000000000000UL}, |
| 256 | {0x0038U, 0x0000000000000000UL}, |
| 257 | {0x0040U, 0x0000000000000000UL}, |
| 258 | {0x0048U, 0x0000000000000000UL}, |
| 259 | {0x0050U, 0x0000000000000000UL}, |
| 260 | {0x0058U, 0x0000000000000000UL}, |
| 261 | {0x0060U, 0x0000000000000000UL}, |
| 262 | {0x0068U, 0x0000000000000000UL}, |
| 263 | {0x0070U, 0x0000000000000000UL}, |
| 264 | {0x0078U, 0x0000000000000000UL}, |
| 265 | {0x0080U, 0x0000000000000000UL}, |
| 266 | {0x0088U, 0x0000000000000000UL}, |
| 267 | {0x0090U, 0x0000000000000000UL}, |
| 268 | {0x0098U, 0x0000000000000000UL}, |
| 269 | {0x00A0U, 0x0000000000000000UL}, |
| 270 | {0x00A8U, 0x0000000000000000UL}, |
| 271 | {0x00B0U, 0x0000000000000000UL}, |
| 272 | {0x00B8U, 0x0000000000000000UL}, |
| 273 | {0x00C0U, 0x0000000000000000UL}, |
| 274 | {0x00C8U, 0x0000000000000000UL}, |
| 275 | {0x00D0U, 0x0000000000000000UL}, |
| 276 | {0x00D8U, 0x0000000000000000UL}, |
| 277 | {0x00E0U, 0x0000000000000000UL}, |
| 278 | {0x00E8U, 0x0000000000000000UL}, |
| 279 | {0x00F0U, 0x0000000000000000UL}, |
| 280 | {0x00F8U, 0x0000000000000000UL}, |
| 281 | {0x0100U, 0x0000000000000000UL}, |
| 282 | {0x0108U, 0x0000000000000000UL}, |
| 283 | {0x0110U, 0x0000000000000000UL}, |
| 284 | {0x0118U, 0x0000000000000000UL}, |
| 285 | {0x0120U, 0x0000000000000000UL}, |
| 286 | {0x0128U, 0x0000000000000000UL}, |
| 287 | {0x0130U, 0x0000000000000000UL}, |
| 288 | {0x0138U, 0x0000000000000000UL}, |
| 289 | {0x0140U, 0x0000000000000000UL}, |
| 290 | {0x0148U, 0x0000000000000000UL}, |
| 291 | {0x0150U, 0x0000000000000000UL}, |
| 292 | {0x0158U, 0x0000000000000000UL}, |
| 293 | {0x0160U, 0x0000000000000000UL}, |
| 294 | {0x0168U, 0x0000000000000000UL}, |
| 295 | {0x0170U, 0x0000000000000000UL}, |
| 296 | {0x0178U, 0x0000000000000000UL}, |
| 297 | {0x0180U, 0x0000000000000000UL}, |
| 298 | {0x0188U, 0x0000000000000000UL}, |
| 299 | {0x0190U, 0x0000000000000000UL}, |
| 300 | {0x0198U, 0x0000000000000000UL}, |
| 301 | {0x01A0U, 0x0000000000000000UL}, |
| 302 | {0x01A8U, 0x0000000000000000UL}, |
| 303 | {0x01B0U, 0x0000000000000000UL}, |
| 304 | {0x01B8U, 0x0000000000000000UL}, |
| 305 | {0x01C0U, 0x001100500C8FFC01UL}, |
| 306 | {0x01C8U, 0x001100500C8FFC01UL}, |
| 307 | {0x01D0U, 0x001100500C8FFC01UL}, |
| 308 | {0x01D8U, 0x001100500C8FFC01UL}, |
| 309 | {0x01E0U, 0x0000000000000000UL}, |
| 310 | {0x01E8U, 0x001200100C803401UL}, |
| 311 | {0x01F0U, 0x001100100C80FC01UL}, |
| 312 | {0x01F8U, 0x0000000000000000UL}, |
| 313 | {0x0200U, 0x0000000000000000UL}, |
| 314 | {0x0208U, 0x001200100C80FC01UL}, |
| 315 | {0x0210U, 0x001100100C80FC01UL}, |
| 316 | {0x0218U, 0x001100100C825801UL}, |
| 317 | {0x0220U, 0x001100100C825801UL}, |
| 318 | {0x0228U, 0x0000000000000000UL}, |
| 319 | {0x0230U, 0x001100100C825801UL}, |
| 320 | {0x0238U, 0x001100100C825801UL}, |
| 321 | {0x0240U, 0x001200100C8BB801UL}, |
| 322 | {0x0248U, 0x001100100C8EA401UL}, |
| 323 | {0x0250U, 0x001200100C8BB801UL}, |
| 324 | {0x0258U, 0x001100100C8EA401UL}, |
| 325 | {0x0260U, 0x001100100C84E401UL}, |
| 326 | {0x0268U, 0x0000000000000000UL}, |
| 327 | {0x0270U, 0x0000000000000000UL}, |
| 328 | {0x0278U, 0x001100100C81F401UL}, |
| 329 | {0x0280U, 0x0000000000000000UL}, |
| 330 | {0x0288U, 0x0000000000000000UL}, |
| 331 | {0x0290U, 0x0000000000000000UL}, |
| 332 | {0x0298U, 0x0000000000000000UL}, |
| 333 | {0x02A0U, 0x0000000000000000UL}, |
| 334 | {0x02A8U, 0x0000000000000000UL}, |
| 335 | {0x02B0U, 0x0000000000000000UL}, |
| 336 | {0x02B8U, 0x001100100C803401UL}, |
| 337 | {0x02C0U, 0x0000000000000000UL}, |
| 338 | {0x02C8U, 0x0000000000000000UL}, |
| 339 | {0x02D0U, 0x0000000000000000UL}, |
| 340 | {0x02D8U, 0x0000000000000000UL}, |
| 341 | {0x02E0U, 0x0000000000000000UL}, |
| 342 | {0x02E8U, 0x001100100C803401UL}, |
| 343 | {0x02F0U, 0x001100300C8FFC01UL}, |
| 344 | {0x02F8U, 0x001100500C8FFC01UL}, |
| 345 | {0x0300U, 0x0000000000000000UL}, |
| 346 | {0x0308U, 0x001100300C8FFC01UL}, |
| 347 | {0x0310U, 0x001100500C8FFC01UL}, |
| 348 | {0x0318U, 0x001200100C803401UL}, |
| 349 | {0x0320U, 0x0000000000000000UL}, |
| 350 | {0x0328U, 0x0000000000000000UL}, |
| 351 | {0x0330U, 0x0000000000000000UL}, |
| 352 | {0x0338U, 0x0000000000000000UL}, |
| 353 | {0x0340U, 0x0000000000000000UL}, |
| 354 | {0x0348U, 0x0000000000000000UL}, |
| 355 | {0x0350U, 0x0000000000000000UL}, |
| 356 | }; |
| 357 | #endif |
| 358 | |
| 359 | static void dbsc_setting(void) |
| 360 | { |
| 361 | uint32_t md = 0; |
| 362 | |
| 363 | /* BUFCAM settings */ |
| 364 | /* DBSC_DBCAM0CNF0 not set */ |
| 365 | io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */ |
| 366 | io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */ |
| 367 | io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */ |
| 368 | io_write_32(DBSC_DBSCHCNT0, 0x080F0037); /* dbschcnt0 */ |
| 369 | /* DBSC_DBSCHCNT1 not set */ |
| 370 | io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */ |
| 371 | io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */ |
| 372 | |
| 373 | md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; |
| 374 | |
| 375 | switch (md) { |
| 376 | case 0x0: |
| 377 | /* DDR3200 */ |
| 378 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 379 | break; |
| 380 | case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ |
| 381 | /* DDR2800 */ |
| 382 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 383 | break; |
| 384 | case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ |
| 385 | /* DDR2400 */ |
| 386 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 387 | break; |
| 388 | default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ |
| 389 | /* DDR1600 */ |
| 390 | io_write_32(DBSC_SCFCTST2, 0x012F1123); |
| 391 | break; |
| 392 | } |
| 393 | |
| 394 | /* QoS Settings */ |
| 395 | io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00); |
| 396 | io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00); |
| 397 | io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000); |
| 398 | io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); |
| 399 | /* DBSC_DBSCHQOS_1_0 not set */ |
| 400 | /* DBSC_DBSCHQOS_1_1 not set */ |
| 401 | /* DBSC_DBSCHQOS_1_2 not set */ |
| 402 | /* DBSC_DBSCHQOS_1_3 not set */ |
| 403 | /* DBSC_DBSCHQOS_2_0 not set */ |
| 404 | /* DBSC_DBSCHQOS_2_1 not set */ |
| 405 | /* DBSC_DBSCHQOS_2_2 not set */ |
| 406 | /* DBSC_DBSCHQOS_2_3 not set */ |
| 407 | /* DBSC_DBSCHQOS_3_0 not set */ |
| 408 | /* DBSC_DBSCHQOS_3_1 not set */ |
| 409 | /* DBSC_DBSCHQOS_3_2 not set */ |
| 410 | /* DBSC_DBSCHQOS_3_3 not set */ |
| 411 | io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300); |
| 412 | io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0); |
| 413 | io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200); |
| 414 | io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100); |
| 415 | /* DBSC_DBSCHQOS_5_0 not set */ |
| 416 | /* DBSC_DBSCHQOS_5_1 not set */ |
| 417 | /* DBSC_DBSCHQOS_5_2 not set */ |
| 418 | /* DBSC_DBSCHQOS_5_3 not set */ |
| 419 | /* DBSC_DBSCHQOS_6_0 not set */ |
| 420 | /* DBSC_DBSCHQOS_6_1 not set */ |
| 421 | /* DBSC_DBSCHQOS_6_2 not set */ |
| 422 | /* DBSC_DBSCHQOS_6_3 not set */ |
| 423 | /* DBSC_DBSCHQOS_7_0 not set */ |
| 424 | /* DBSC_DBSCHQOS_7_1 not set */ |
| 425 | /* DBSC_DBSCHQOS_7_2 not set */ |
| 426 | /* DBSC_DBSCHQOS_7_3 not set */ |
| 427 | /* DBSC_DBSCHQOS_8_0 not set */ |
| 428 | /* DBSC_DBSCHQOS_8_1 not set */ |
| 429 | /* DBSC_DBSCHQOS_8_2 not set */ |
| 430 | /* DBSC_DBSCHQOS_8_3 not set */ |
| 431 | io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300); |
| 432 | io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0); |
| 433 | io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200); |
| 434 | io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100); |
| 435 | /* DBSC_DBSCHQOS_10_0 not set */ |
| 436 | /* DBSC_DBSCHQOS_10_1 not set */ |
| 437 | /* DBSC_DBSCHQOS_10_2 not set */ |
| 438 | /* DBSC_DBSCHQOS_10_3 not set */ |
| 439 | /* DBSC_DBSCHQOS_11_0 not set */ |
| 440 | /* DBSC_DBSCHQOS_11_1 not set */ |
| 441 | /* DBSC_DBSCHQOS_11_2 not set */ |
| 442 | /* DBSC_DBSCHQOS_11_3 not set */ |
| 443 | /* DBSC_DBSCHQOS_12_0 not set */ |
| 444 | /* DBSC_DBSCHQOS_12_1 not set */ |
| 445 | /* DBSC_DBSCHQOS_12_2 not set */ |
| 446 | /* DBSC_DBSCHQOS_12_3 not set */ |
| 447 | io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100); |
| 448 | io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0); |
| 449 | io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0); |
| 450 | io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040); |
| 451 | io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0); |
| 452 | io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0); |
| 453 | io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080); |
| 454 | io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040); |
| 455 | io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040); |
| 456 | io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030); |
| 457 | io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020); |
| 458 | io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010); |
| 459 | } |
| 460 | |
| 461 | void qos_init_m3_v10(void) |
| 462 | { |
| 463 | dbsc_setting(); |
| 464 | |
| 465 | /* DRAM Split Address mapping */ |
| 466 | #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH |
| 467 | #if RCAR_LSI == RCAR_M3 |
| 468 | #error "Don't set DRAM Split 4ch(M3)" |
| 469 | #else |
| 470 | ERROR("DRAM Split 4ch not supported.(M3)"); |
| 471 | panic(); |
| 472 | #endif |
| 473 | #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \ |
| 474 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 475 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 476 | io_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 477 | io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
| 478 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 479 | | ADSPLCR0_AREA(0x1CU) |
| 480 | | ADSPLCR0_SWP); |
| 481 | io_write_32(AXI_ADSPLCR2, 0x089A0000U); |
| 482 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 483 | #else |
| 484 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 485 | #endif |
| 486 | |
| 487 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 488 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 489 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 490 | #endif |
| 491 | |
| 492 | /* Resource Alloc setting */ |
| 493 | io_write_32(RALLOC_RAS, 0x00000028U); |
| 494 | io_write_32(RALLOC_FIXTH, 0x000F0005U); |
| 495 | io_write_32(RALLOC_REGGD, 0x00000000U); |
| 496 | io_write_64(RALLOC_DANN, 0x0101010102020201UL); |
| 497 | io_write_32(RALLOC_DANT, 0x00100804U); |
| 498 | io_write_32(RALLOC_EC, 0x00000000U); |
| 499 | io_write_64(RALLOC_EMS, 0x0000000000000000UL); |
| 500 | io_write_32(RALLOC_FSS, 0x000003e8U); |
| 501 | io_write_32(RALLOC_INSFC, 0xC7840001U); |
| 502 | io_write_32(RALLOC_BERR, 0x00000000U); |
| 503 | io_write_32(RALLOC_RACNT0, 0x00000000U); |
| 504 | |
| 505 | /* MSTAT setting */ |
| 506 | io_write_32(MSTAT_SL_INIT, |
| 507 | SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); |
| 508 | io_write_32(MSTAT_REF_ARS, 0x00330000U); |
| 509 | |
| 510 | /* MSTAT SRAM setting */ |
| 511 | { |
| 512 | uint32_t i; |
| 513 | |
| 514 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 515 | io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, |
| 516 | mstat_fix[i].value); |
| 517 | io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, |
| 518 | mstat_fix[i].value); |
| 519 | } |
| 520 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 521 | io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, |
| 522 | mstat_be[i].value); |
| 523 | io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, |
| 524 | mstat_be[i].value); |
| 525 | } |
| 526 | } |
| 527 | |
| 528 | /* 3DG bus Leaf setting */ |
| 529 | io_write_32(0xFD820808U, 0x00001234U); |
| 530 | io_write_32(0xFD820800U, 0x00000006U); |
| 531 | io_write_32(0xFD821800U, 0x00000006U); |
| 532 | io_write_32(0xFD822800U, 0x00000006U); |
| 533 | io_write_32(0xFD823800U, 0x00000006U); |
| 534 | io_write_32(0xFD824800U, 0x00000006U); |
| 535 | io_write_32(0xFD825800U, 0x00000006U); |
| 536 | io_write_32(0xFD826800U, 0x00000006U); |
| 537 | io_write_32(0xFD827800U, 0x00000006U); |
| 538 | |
| 539 | /* RT bus Leaf setting */ |
| 540 | io_write_32(0xFFC50800U, 0x00000000U); |
| 541 | io_write_32(0xFFC51800U, 0x00000000U); |
| 542 | |
| 543 | /* Resource Alloc start */ |
| 544 | io_write_32(RALLOC_RAEN, 0x00000001U); |
| 545 | |
| 546 | /* MSTAT start */ |
| 547 | io_write_32(MSTAT_STATQC, 0x00000001U); |
| 548 | #else |
| 549 | NOTICE("BL2: QoS is None\n"); |
| 550 | |
| 551 | /* Resource Alloc setting */ |
| 552 | io_write_32(RALLOC_EC, 0x00000000U); |
| 553 | /* Resource Alloc start */ |
| 554 | io_write_32(RALLOC_RAEN, 0x00000001U); |
| 555 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 556 | } |