| Pankaj Gupta | 44392ea | 2020-12-09 14:02:38 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef SFP_H |
| 9 | #define SFP_H |
| 10 | |
| 11 | #include <endian.h> |
| 12 | #include <lib/mmio.h> |
| 13 | |
| 14 | /* SFP Configuration Register Offsets */ |
| 15 | #define SFP_INGR_OFFSET U(0x20) |
| 16 | #define SFP_SVHESR_OFFSET U(0x24) |
| 17 | #define SFP_SFPCR_OFFSET U(0x28) |
| 18 | #define SFP_VER_OFFSET U(0x38) |
| 19 | |
| 20 | /* SFP Hamming register masks for OTPMK and DRV */ |
| 21 | #define SFP_SVHESR_DRV_MASK U(0x7F) |
| 22 | #define SFP_SVHESR_OTPMK_MASK U(0x7FC00) |
| 23 | |
| 24 | /* SFP commands */ |
| 25 | #define SFP_INGR_READFB_CMD U(0x1) |
| 26 | #define SFP_INGR_PROGFB_CMD U(0x2) |
| 27 | #define SFP_INGR_ERROR_MASK U(0x100) |
| 28 | |
| 29 | /* SFPCR Masks */ |
| 30 | #define SFP_SFPCR_WD U(0x80000000) |
| 31 | #define SFP_SFPCR_WDL U(0x40000000) |
| 32 | |
| 33 | /* SFPCR Masks */ |
| 34 | #define SFP_SFPCR_WD U(0x80000000) |
| 35 | #define SFP_SFPCR_WDL U(0x40000000) |
| 36 | |
| 37 | #define SFP_FUSE_REGS_OFFSET U(0x200) |
| 38 | |
| 39 | #ifdef NXP_SFP_VER_3_4 |
| 40 | #define OSPR0_SC_MASK U(0xC000FE35) |
| 41 | #elif defined(NXP_SFP_VER_3_2) |
| 42 | #define OSPR0_SC_MASK U(0x0000E035) |
| 43 | #endif |
| 44 | |
| 45 | #if defined(NXP_SFP_VER_3_4) |
| 46 | #define OSPR_KEY_REVOC_SHIFT U(9) |
| 47 | #define OSPR_KEY_REVOC_MASK U(0x0000fe00) |
| 48 | #elif defined(NXP_SFP_VER_3_2) |
| 49 | #define OSPR_KEY_REVOC_SHIFT U(13) |
| 50 | #define OSPR_KEY_REVOC_MASK U(0x0000e000) |
| 51 | #endif /* NXP_SFP_VER_3_4 */ |
| 52 | |
| 53 | #define OSPR1_MC_MASK U(0xFFFF0000) |
| 54 | #define OSPR1_DBG_LVL_MASK U(0x00000007) |
| 55 | |
| 56 | #define OSPR_ITS_MASK U(0x00000004) |
| 57 | #define OSPR_WP_MASK U(0x00000001) |
| 58 | |
| 59 | #define MAX_OEM_UID U(5) |
| 60 | #define SRK_HASH_SIZE U(32) |
| 61 | |
| 62 | /* SFP CCSR Register Map */ |
| 63 | struct sfp_ccsr_regs_t { |
| 64 | uint32_t ospr; /* 0x200 OSPR0 */ |
| 65 | uint32_t ospr1; /* 0x204 OSPR1 */ |
| 66 | uint32_t dcv[2]; /* 0x208 Debug Challenge Value */ |
| 67 | uint32_t drv[2]; /* 0x210 Debug Response Value */ |
| 68 | uint32_t fswpr; /* 0x218 FSL Section Write Protect */ |
| 69 | uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */ |
| 70 | uint32_t isbcr; /* 0x224 ISBC Configuration */ |
| 71 | uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */ |
| 72 | uint32_t otpmk[8]; /* 0x234 OTPMK */ |
| 73 | uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]; |
| 74 | /* 0x254 Super Root Key Hash */ |
| 75 | uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */ |
| 76 | }; |
| 77 | |
| 78 | uintptr_t get_sfp_addr(void); |
| 79 | void sfp_init(uintptr_t nxp_sfp_addr); |
| 80 | uint32_t *get_sfp_srk_hash(void); |
| 81 | int sfp_check_its(void); |
| 82 | int sfp_check_oem_wp(void); |
| 83 | uint32_t get_key_revoc(void); |
| 84 | void set_sfp_wr_disable(void); |
| 85 | int sfp_program_fuses(void); |
| 86 | |
| 87 | uint32_t sfp_read_oem_uid(uint8_t oem_uid); |
| 88 | uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val); |
| 89 | |
| 90 | #ifdef NXP_SFP_BE |
| 91 | #define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) |
| 92 | #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) |
| 93 | #elif defined(NXP_SFP_LE) |
| 94 | #define sfp_read32(a) mmio_read_32((uintptr_t)(a)) |
| 95 | #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) |
| 96 | #else |
| 97 | #error Please define CCSR SFP register endianness |
| 98 | #endif |
| 99 | |
| 100 | #endif/* SFP_H */ |