developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 1 | /* |
Deepika Bhavnani | 813864e | 2019-12-13 10:50:55 -0600 | [diff] [blame] | 2 | * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/interrupt_props.h> |
| 11 | #include <drivers/arm/gic_common.h> |
| 12 | #include <lib/utils_def.h> |
| 13 | |
Koan-Sin Tan | 1d2b639 | 2016-04-18 15:17:57 +0800 | [diff] [blame] | 14 | #include "mt8173_def.h" |
| 15 | |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 16 | /******************************************************************************* |
| 17 | * Platform binary types for linking |
| 18 | ******************************************************************************/ |
| 19 | #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" |
| 20 | #define PLATFORM_LINKER_ARCH aarch64 |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * Generic platform constants |
| 24 | ******************************************************************************/ |
| 25 | |
| 26 | /* Size of cacheable stacks */ |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 27 | #if defined(IMAGE_BL1) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 28 | #define PLATFORM_STACK_SIZE 0x440 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 29 | #elif defined(IMAGE_BL2) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 30 | #define PLATFORM_STACK_SIZE 0x400 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 31 | #elif defined(IMAGE_BL31) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 32 | #define PLATFORM_STACK_SIZE 0x800 |
Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 33 | #elif defined(IMAGE_BL32) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 34 | #define PLATFORM_STACK_SIZE 0x440 |
| 35 | #endif |
| 36 | |
| 37 | #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" |
| 38 | |
| 39 | #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 40 | #define PLAT_MAX_PWR_LVL U(2) |
| 41 | #define PLAT_MAX_RET_STATE U(1) |
| 42 | #define PLAT_MAX_OFF_STATE U(2) |
Deepika Bhavnani | 813864e | 2019-12-13 10:50:55 -0600 | [diff] [blame] | 43 | #define PLATFORM_SYSTEM_COUNT U(1) |
| 44 | #define PLATFORM_CLUSTER_COUNT U(2) |
| 45 | #define PLATFORM_CLUSTER0_CORE_COUNT U(4) |
| 46 | #define PLATFORM_CLUSTER1_CORE_COUNT U(2) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 47 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ |
| 48 | PLATFORM_CLUSTER0_CORE_COUNT) |
Deepika Bhavnani | 813864e | 2019-12-13 10:50:55 -0600 | [diff] [blame] | 49 | #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 50 | #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ |
| 51 | PLATFORM_CLUSTER_COUNT + \ |
| 52 | PLATFORM_CORE_COUNT) |
| 53 | |
Hsin-Yi Wang | e0bf305 | 2020-08-27 13:48:48 +0800 | [diff] [blame^] | 54 | #define SOC_CHIP_ID U(0x8173) |
| 55 | |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 56 | /******************************************************************************* |
| 57 | * Platform memory map related constants |
| 58 | ******************************************************************************/ |
developer | 4419325 | 2016-03-04 20:18:58 +0800 | [diff] [blame] | 59 | /* |
| 60 | * MT8173 SRAM memory layout |
| 61 | * 0x100000 +-------------------+ |
| 62 | * | shared mem (4KB) | |
| 63 | * 0x101000 +-------------------+ |
| 64 | * | | |
| 65 | * | BL3-1 (124KB) | |
| 66 | * | | |
| 67 | * 0x120000 +-------------------+ |
| 68 | * | reserved (64KB) | |
| 69 | * 0x130000 +-------------------+ |
| 70 | */ |
| 71 | /* TF txet, ro, rw, xlat table, coherent memory ... etc. |
| 72 | * Size: release: 128KB, debug: 128KB |
| 73 | */ |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 74 | #define TZRAM_BASE (0x100000) |
| 75 | #if DEBUG |
| 76 | #define TZRAM_SIZE (0x20000) |
| 77 | #else |
| 78 | #define TZRAM_SIZE (0x20000) |
| 79 | #endif |
| 80 | |
developer | 4419325 | 2016-03-04 20:18:58 +0800 | [diff] [blame] | 81 | /* Reserved: 64KB */ |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 82 | #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) |
| 83 | #define TZRAM2_SIZE (0x10000) |
| 84 | |
| 85 | /******************************************************************************* |
| 86 | * BL31 specific defines. |
| 87 | ******************************************************************************/ |
| 88 | /* |
| 89 | * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if |
| 90 | * present). BL31_BASE is calculated using the current BL3-1 debug size plus a |
| 91 | * little space for growth. |
| 92 | */ |
| 93 | #define BL31_BASE (TZRAM_BASE + 0x1000) |
| 94 | #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 95 | #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) |
| 96 | |
| 97 | /******************************************************************************* |
| 98 | * Platform specific page table and MMU setup constants |
| 99 | ******************************************************************************/ |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 100 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 101 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
developer | 65014b8 | 2015-04-13 14:47:57 +0800 | [diff] [blame] | 102 | #define MAX_XLAT_TABLES 4 |
| 103 | #define MAX_MMAP_REGIONS 16 |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * Declarations and constants to access the mailboxes safely. Each mailbox is |
| 107 | * aligned on the biggest cache line size in the platform. This is known only |
| 108 | * to the platform as it might have a combination of integrated and external |
| 109 | * caches. Such alignment ensures that two maiboxes do not sit on the same cache |
| 110 | * line at any cache level. They could belong to different cpus/clusters & |
| 111 | * get written while being protected by different locks causing corruption of |
| 112 | * a valid mailbox address. |
| 113 | ******************************************************************************/ |
| 114 | #define CACHE_WRITEBACK_SHIFT 6 |
| 115 | #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) |
| 116 | |
Koan-Sin Tan | 1d2b639 | 2016-04-18 15:17:57 +0800 | [diff] [blame] | 117 | |
| 118 | #define PLAT_ARM_GICD_BASE BASE_GICD_BASE |
| 119 | #define PLAT_ARM_GICC_BASE BASE_GICC_BASE |
| 120 | |
Jeenu Viswambharan | 392cbb3 | 2017-09-29 11:14:51 +0100 | [diff] [blame] | 121 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ |
| 122 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 123 | GIC_INTR_CFG_EDGE), \ |
| 124 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 125 | GIC_INTR_CFG_EDGE), \ |
| 126 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 127 | GIC_INTR_CFG_EDGE), \ |
| 128 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 129 | GIC_INTR_CFG_EDGE), \ |
| 130 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 131 | GIC_INTR_CFG_EDGE), \ |
| 132 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 133 | GIC_INTR_CFG_EDGE), \ |
| 134 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 135 | GIC_INTR_CFG_EDGE), \ |
| 136 | INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 137 | GIC_INTR_CFG_EDGE) |
Koan-Sin Tan | 1d2b639 | 2016-04-18 15:17:57 +0800 | [diff] [blame] | 138 | |
Jeenu Viswambharan | 392cbb3 | 2017-09-29 11:14:51 +0100 | [diff] [blame] | 139 | #define PLAT_ARM_G0_IRQ_PROPS(grp) |
Koan-Sin Tan | 1d2b639 | 2016-04-18 15:17:57 +0800 | [diff] [blame] | 140 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 141 | #endif /* PLATFORM_DEF_H */ |