| Leif Lindholm | 9a7bf65 | 2021-03-10 13:23:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <cpu_macros.S> |
| 9 | #include <qemu_max.h> |
| 10 | |
| 11 | func qemu_max_core_pwr_dwn |
| 12 | /* --------------------------------------------- |
| 13 | * Disable the Data Cache. |
| 14 | * --------------------------------------------- |
| 15 | */ |
| 16 | mrs x1, sctlr_el3 |
| 17 | bic x1, x1, #SCTLR_C_BIT |
| 18 | msr sctlr_el3, x1 |
| 19 | isb |
| 20 | |
| 21 | /* --------------------------------------------- |
| 22 | * Flush L1 cache to L2. |
| 23 | * --------------------------------------------- |
| 24 | */ |
| 25 | mov x18, lr |
| 26 | mov x0, #DCCISW |
| 27 | bl dcsw_op_level1 |
| 28 | mov lr, x18 |
| 29 | ret |
| 30 | endfunc qemu_max_core_pwr_dwn |
| 31 | |
| 32 | func qemu_max_cluster_pwr_dwn |
| 33 | /* --------------------------------------------- |
| 34 | * Disable the Data Cache. |
| 35 | * --------------------------------------------- |
| 36 | */ |
| 37 | mrs x1, sctlr_el3 |
| 38 | bic x1, x1, #SCTLR_C_BIT |
| 39 | msr sctlr_el3, x1 |
| 40 | isb |
| 41 | |
| 42 | /* --------------------------------------------- |
| 43 | * Flush all caches to PoC. |
| 44 | * --------------------------------------------- |
| 45 | */ |
| 46 | mov x0, #DCCISW |
| 47 | b dcsw_op_all |
| 48 | endfunc qemu_max_cluster_pwr_dwn |
| 49 | |
| 50 | #if REPORT_ERRATA |
| 51 | /* |
| 52 | * Errata printing function for QEMU "max". Must follow AAPCS. |
| 53 | */ |
| 54 | func qemu_max_errata_report |
| 55 | ret |
| 56 | endfunc qemu_max_errata_report |
| 57 | #endif |
| 58 | |
| 59 | /* --------------------------------------------- |
| 60 | * This function provides cpu specific |
| 61 | * register information for crash reporting. |
| 62 | * It needs to return with x6 pointing to |
| 63 | * a list of register names in ascii and |
| 64 | * x8 - x15 having values of registers to be |
| 65 | * reported. |
| 66 | * --------------------------------------------- |
| 67 | */ |
| 68 | .section .rodata.qemu_max_regs, "aS" |
| 69 | qemu_max_regs: /* The ascii list of register names to be reported */ |
| 70 | .asciz "" /* no registers to report */ |
| 71 | |
| 72 | func qemu_max_cpu_reg_dump |
| 73 | adr x6, qemu_max_regs |
| 74 | ret |
| 75 | endfunc qemu_max_cpu_reg_dump |
| 76 | |
| 77 | |
| 78 | /* cpu_ops for QEMU MAX */ |
| 79 | declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \ |
| 80 | qemu_max_core_pwr_dwn, \ |
| 81 | qemu_max_cluster_pwr_dwn |