Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. |
Tanmay Shah | fdae9e8 | 2022-08-26 15:06:00 -0700 | [diff] [blame] | 3 | * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. |
Maheedhar Bollapalli | ae8e013 | 2024-07-24 09:54:15 +0530 | [diff] [blame] | 4 | * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #ifndef VERSAL_DEF_H |
| 10 | #define VERSAL_DEF_H |
| 11 | |
Manish V Badarkhe | 5586151 | 2020-03-27 13:25:51 +0000 | [diff] [blame] | 12 | #include <plat/arm/common/smccc_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 13 | #include <plat/common/common_def.h> |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 14 | |
Akshay Belsare | 589ccce | 2023-05-08 19:00:53 +0530 | [diff] [blame] | 15 | #define PLATFORM_MASK GENMASK(27U, 24U) |
| 16 | #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) |
| 17 | |
Tanmay Shah | fdae9e8 | 2022-08-26 15:06:00 -0700 | [diff] [blame] | 18 | /* number of interrupt handlers. increase as required */ |
| 19 | #define MAX_INTR_EL3 2 |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 20 | /* List all consoles */ |
| 21 | #define VERSAL_CONSOLE_ID_pl011 1 |
| 22 | #define VERSAL_CONSOLE_ID_pl011_0 1 |
| 23 | #define VERSAL_CONSOLE_ID_pl011_1 2 |
| 24 | #define VERSAL_CONSOLE_ID_dcc 3 |
| 25 | |
Michal Simek | c56e548 | 2023-09-27 13:58:06 +0200 | [diff] [blame] | 26 | #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 27 | |
Maheedhar Bollapalli | ae8e013 | 2024-07-24 09:54:15 +0530 | [diff] [blame] | 28 | /* List of platforms */ |
| 29 | #define VERSAL_SILICON U(0) |
| 30 | #define VERSAL_SPP U(1) |
| 31 | #define VERSAL_EMU U(2) |
| 32 | #define VERSAL_QEMU U(3) |
Akshay Belsare | fc74bf1 | 2024-09-13 15:56:00 +0530 | [diff] [blame] | 33 | #define VERSAL_COSIM U(7) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 34 | |
| 35 | /* Firmware Image Package */ |
| 36 | #define VERSAL_PRIMARY_CPU 0 |
| 37 | |
| 38 | /******************************************************************************* |
| 39 | * memory map related constants |
| 40 | ******************************************************************************/ |
| 41 | #define DEVICE0_BASE 0xFF000000 |
| 42 | #define DEVICE0_SIZE 0x00E00000 |
| 43 | #define DEVICE1_BASE 0xF9000000 |
| 44 | #define DEVICE1_SIZE 0x00800000 |
| 45 | |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 46 | /******************************************************************************* |
| 47 | * IRQ constants |
| 48 | ******************************************************************************/ |
Abhyuday Godhasara | 096f5cc | 2021-08-13 06:45:32 -0700 | [diff] [blame] | 49 | #define VERSAL_IRQ_SEC_PHY_TIMER U(29) |
Prasad Kummari | 6dee9fb | 2023-10-31 15:20:00 +0530 | [diff] [blame] | 50 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 51 | |
| 52 | /******************************************************************************* |
Tejas Patel | 54d1319 | 2019-02-27 18:44:55 +0530 | [diff] [blame] | 53 | * CCI-400 related constants |
| 54 | ******************************************************************************/ |
| 55 | #define PLAT_ARM_CCI_BASE 0xFD000000 |
Michal Simek | 467e16e | 2023-04-14 08:39:49 +0200 | [diff] [blame] | 56 | #define PLAT_ARM_CCI_SIZE 0x00100000 |
Tejas Patel | 54d1319 | 2019-02-27 18:44:55 +0530 | [diff] [blame] | 57 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 58 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 |
| 59 | |
| 60 | /******************************************************************************* |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 61 | * UART related constants |
| 62 | ******************************************************************************/ |
| 63 | #define VERSAL_UART0_BASE 0xFF000000 |
| 64 | #define VERSAL_UART1_BASE 0xFF010000 |
| 65 | |
Michal Simek | c56e548 | 2023-09-27 13:58:06 +0200 | [diff] [blame] | 66 | #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) |
| 67 | # define UART_BASE VERSAL_UART0_BASE |
| 68 | #elif CONSOLE_IS(pl011_1) |
| 69 | # define UART_BASE VERSAL_UART1_BASE |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 70 | #else |
| 71 | # error "invalid VERSAL_CONSOLE" |
| 72 | #endif |
| 73 | |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 74 | /******************************************************************************* |
| 75 | * Platform related constants |
| 76 | ******************************************************************************/ |
Maheedhar Bollapalli | ae8e013 | 2024-07-24 09:54:15 +0530 | [diff] [blame] | 77 | #define UART_BAUDRATE 115200 |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 78 | |
| 79 | /* Access control register defines */ |
| 80 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 81 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 82 | |
| 83 | /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ |
| 84 | #define CRF_BASE 0xFD1A0000 |
| 85 | #define CRF_SIZE 0x00600000 |
| 86 | |
| 87 | /* CRF registers and bitfields */ |
| 88 | #define CRF_RST_APU (CRF_BASE + 0X00000300) |
| 89 | |
| 90 | #define CRF_RST_APU_ACPU_RESET (1 << 0) |
| 91 | #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) |
| 92 | |
Prasad Kummari | 2038bd6 | 2023-12-14 10:52:24 +0530 | [diff] [blame] | 93 | /* IOU SCNTRS */ |
| 94 | #define IOU_SCNTRS_BASE U(0xFF140000) |
| 95 | #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) |
| 96 | |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 97 | /* APU registers and bitfields */ |
Abhyuday Godhasara | edc38ae | 2021-08-04 23:58:46 -0700 | [diff] [blame] | 98 | #define FPD_APU_BASE 0xFD5C0000U |
| 99 | #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) |
| 100 | #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) |
| 101 | #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) |
| 102 | #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 103 | |
Abhyuday Godhasara | edc38ae | 2021-08-04 23:58:46 -0700 | [diff] [blame] | 104 | #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U |
| 105 | #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U |
| 106 | #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 107 | |
Venkatesh Yadav Abbarapu | 9156ffd | 2020-01-22 21:23:20 -0700 | [diff] [blame] | 108 | /* PMC registers and bitfields */ |
Abhyuday Godhasara | edc38ae | 2021-08-04 23:58:46 -0700 | [diff] [blame] | 109 | #define PMC_GLOBAL_BASE 0xF1110000U |
| 110 | #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) |
Venkatesh Yadav Abbarapu | 9156ffd | 2020-01-22 21:23:20 -0700 | [diff] [blame] | 111 | |
Siva Durga Prasad Paladugu | fe4af66 | 2018-09-25 18:44:58 +0530 | [diff] [blame] | 112 | #endif /* VERSAL_DEF_H */ |