| Jiafei Pan | 10357d9 | 2022-01-20 17:42:39 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2018-2022 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | #include <string.h> |
| 10 | |
| 11 | #include <common/debug.h> |
| 12 | #include <ddr.h> |
| 13 | #include <lib/utils.h> |
| 14 | |
| 15 | #include <errata.h> |
| 16 | #include <platform_def.h> |
| 17 | |
| 18 | #ifdef CONFIG_STATIC_DDR |
| 19 | const struct ddr_cfg_regs static_1600 = { |
| 20 | .cs[0].config = U(0x80010412), |
| 21 | .cs[0].bnds = U(0x7F), |
| 22 | .sdram_cfg[0] = U(0xE50C0008), |
| 23 | .sdram_cfg[1] = U(0x00401010), |
| 24 | .sdram_cfg[2] = U(0x1), |
| 25 | .timing_cfg[0] = U(0xFA550018), |
| 26 | .timing_cfg[1] = U(0xBAB40C52), |
| 27 | .timing_cfg[2] = U(0x0048C11C), |
| 28 | .timing_cfg[3] = U(0x01111000), |
| 29 | .timing_cfg[4] = U(0x00000002), |
| 30 | .timing_cfg[5] = U(0x03401400), |
| 31 | .timing_cfg[6] = U(0x0), |
| 32 | .timing_cfg[7] = U(0x23300000), |
| 33 | .timing_cfg[8] = U(0x02116600), |
| 34 | .timing_cfg[9] = U(0x0), |
| 35 | .dq_map[0] = U(0x0), |
| 36 | .dq_map[1] = U(0x0), |
| 37 | .dq_map[2] = U(0x0), |
| 38 | .dq_map[3] = U(0x0), |
| 39 | .sdram_mode[0] = U(0x01010210), |
| 40 | .sdram_mode[1] = U(0x0), |
| 41 | .sdram_mode[8] = U(0x00000500), |
| 42 | .sdram_mode[9] = U(0x04000000), |
| 43 | .interval = U(0x18600618), |
| 44 | .zq_cntl = U(0x8A090705), |
| 45 | .ddr_sr_cntr = U(0x0), |
| 46 | .clk_cntl = U(0x2000000), |
| 47 | .cdr[0] = U(0x80040000), |
| 48 | .cdr[1] = U(0xC1), |
| 49 | .wrlvl_cntl[0] = U(0x86550607), |
| 50 | .wrlvl_cntl[1] = U(0x07070708), |
| 51 | .wrlvl_cntl[2] = U(0x0808088), |
| 52 | }; |
| 53 | |
| 54 | long long board_static_ddr(struct ddr_info *priv) |
| 55 | { |
| 56 | memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600)); |
| 57 | |
| 58 | return 0x80000000ULL; |
| 59 | } |
| 60 | #else /* ifndef CONFIG_STATIC_DDR */ |
| 61 | static const struct rc_timing rcz[] = { |
| 62 | {U(1600), U(8), U(7)}, |
| 63 | {U(2100), U(8), U(7)}, |
| 64 | {} |
| 65 | }; |
| 66 | |
| 67 | static const struct board_timing ram[] = { |
| 68 | {U(0x1f), rcz, U(0x01010101), U(0x01010101)}, |
| 69 | }; |
| 70 | |
| 71 | int ddr_board_options(struct ddr_info *priv) |
| 72 | { |
| 73 | int ret; |
| 74 | struct memctl_opt *popts = &priv->opt; |
| 75 | |
| 76 | ret = cal_board_params(priv, ram, ARRAY_SIZE(ram)); |
| 77 | if (ret != 0) { |
| 78 | return ret; |
| 79 | } |
| 80 | |
| 81 | popts->bstopre = 0; |
| 82 | popts->half_strength_drive_en = 1; |
| 83 | popts->cpo_sample = U(0x46); |
| 84 | popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_50ohm); |
| 85 | popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_50ohm) | |
| 86 | DDR_CDR2_VREF_TRAIN_EN; |
| 87 | popts->output_driver_impedance = 1; |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | /* DDR model number: MT40A512M16JY-083E:B */ |
| 93 | struct dimm_params ddr_raw_timing = { |
| 94 | .n_ranks = U(1), |
| 95 | .rank_density = ULL(4294967296), |
| 96 | .capacity = ULL(4294967296), |
| 97 | .primary_sdram_width = U(64), |
| 98 | .ec_sdram_width = U(8), |
| 99 | .rdimm = U(0), |
| 100 | .mirrored_dimm = U(0), |
| 101 | .n_row_addr = U(16), |
| 102 | .n_col_addr = U(10), |
| 103 | .bank_group_bits = U(1), |
| 104 | .edc_config = U(2), |
| 105 | .burst_lengths_bitmask = U(0x0c), |
| 106 | .tckmin_x_ps = 750, |
| 107 | .tckmax_ps = 1900, |
| 108 | .caslat_x = U(0x0001FFE00), |
| 109 | .taa_ps = 13500, |
| 110 | .trcd_ps = 13500, |
| 111 | .trp_ps = 13500, |
| 112 | .tras_ps = 33000, |
| 113 | .trc_ps = 46500, |
| 114 | .twr_ps = 15000, |
| 115 | .trfc1_ps = 350000, |
| 116 | .trfc2_ps = 260000, |
| 117 | .trfc4_ps = 160000, |
| 118 | .tfaw_ps = 30000, |
| 119 | .trrds_ps = 5300, |
| 120 | .trrdl_ps = 6400, |
| 121 | .tccdl_ps = 5355, |
| 122 | .refresh_rate_ps = U(7800000), |
| 123 | .dq_mapping[0] = U(0x0), |
| 124 | .dq_mapping[1] = U(0x0), |
| 125 | .dq_mapping[2] = U(0x0), |
| 126 | .dq_mapping[3] = U(0x0), |
| 127 | .dq_mapping[4] = U(0x0), |
| 128 | .dq_mapping_ors = U(0), |
| 129 | .rc = U(0x1f), |
| 130 | }; |
| 131 | |
| 132 | int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf) |
| 133 | { |
| 134 | static const char dimm_model[] = "Fixed DDR on board"; |
| 135 | |
| 136 | conf->dimm_in_use[0] = 1; |
| 137 | memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params)); |
| 138 | memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); |
| 139 | |
| 140 | return 1; |
| 141 | } |
| 142 | #endif /* ifdef CONFIG_STATIC_DDR */ |
| 143 | |
| 144 | long long init_ddr(void) |
| 145 | { |
| 146 | int spd_addr[] = {NXP_SPD_EEPROM0}; |
| 147 | struct ddr_info info; |
| 148 | struct sysinfo sys; |
| 149 | long long dram_size; |
| 150 | |
| 151 | zeromem(&sys, sizeof(sys)); |
| 152 | if (get_clocks(&sys)) { |
| 153 | ERROR("System clocks are not set\n"); |
| 154 | assert(0); |
| 155 | } |
| 156 | debug("platform clock %lu\n", sys.freq_platform); |
| 157 | debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); |
| 158 | debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); |
| 159 | |
| 160 | zeromem(&info, sizeof(struct ddr_info)); |
| 161 | info.num_ctlrs = 1; |
| 162 | info.dimm_on_ctlr = 1; |
| 163 | info.clk = get_ddr_freq(&sys, 0); |
| 164 | info.spd_addr = spd_addr; |
| 165 | info.ddr[0] = (void *)NXP_DDR_ADDR; |
| 166 | |
| 167 | dram_size = dram_init(&info); |
| 168 | if (dram_size < 0) { |
| 169 | ERROR("DDR init failed.\n"); |
| 170 | } |
| 171 | |
| 172 | #ifdef ERRATA_SOC_A008850 |
| 173 | erratum_a008850_post(); |
| 174 | #endif |
| 175 | |
| 176 | return dram_size; |
| 177 | } |