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git01.mediatek.com / filogic / atf / e05753c644652c477ac9c209319cb88cad03055c / . / plat / arm / board / rdn2 / rdn2_topology.c
blob: 89300f88224fc37ab1cbea0772630f75a83f68e0 [file] [log] [blame]
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]1/*
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <plat/arm/common/plat_arm.h>
8#include <plat/arm/css/common/css_pm.h>
9
10/******************************************************************************
11 * The power domain tree descriptor.
12 ******************************************************************************/
13const unsigned char rd_n2_pd_tree_desc[] = {
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]14 (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]15 CSS_SGI_MAX_CPUS_PER_CLUSTER,
16 CSS_SGI_MAX_CPUS_PER_CLUSTER,
17 CSS_SGI_MAX_CPUS_PER_CLUSTER,
18 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]19#if (CSS_SGI_PLATFORM_VARIANT != 2 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]20 CSS_SGI_MAX_CPUS_PER_CLUSTER,
21 CSS_SGI_MAX_CPUS_PER_CLUSTER,
22 CSS_SGI_MAX_CPUS_PER_CLUSTER,
23 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]24#endif
25#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]26 CSS_SGI_MAX_CPUS_PER_CLUSTER,
27 CSS_SGI_MAX_CPUS_PER_CLUSTER,
28 CSS_SGI_MAX_CPUS_PER_CLUSTER,
29 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]30#endif
31#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]32 CSS_SGI_MAX_CPUS_PER_CLUSTER,
33 CSS_SGI_MAX_CPUS_PER_CLUSTER,
34 CSS_SGI_MAX_CPUS_PER_CLUSTER,
35 CSS_SGI_MAX_CPUS_PER_CLUSTER,
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]36#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]37};
38
39/*******************************************************************************
40 * This function returns the topology tree information.
41 ******************************************************************************/
42const unsigned char *plat_get_power_domain_tree_desc(void)
43{
44 return rd_n2_pd_tree_desc;
45}
46
47/*******************************************************************************
48 * The array mapping platform core position (implemented by plat_my_core_pos())
49 * to the SCMI power domain ID implemented by SCP.
50 ******************************************************************************/
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]51#if (CSS_SGI_PLATFORM_VARIANT == 2)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]52const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
53 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
54 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
55 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
56 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]57#if (CSS_SGI_CHIP_COUNT > 1)
58 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
59 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
60 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
61 (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
62#endif
63#if (CSS_SGI_CHIP_COUNT > 2)
64 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
65 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
66 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
67 (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
68#endif
69#if (CSS_SGI_CHIP_COUNT > 3)
70 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
71 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
72 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
73 (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
74#endif
75};
76#else
77const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
78 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
79 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
80 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
81 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]82 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
83 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
84 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
85 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]86#if (CSS_SGI_PLATFORM_VARIANT == 0)
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]87 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
88 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
89 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
90 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
91 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
92 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
93 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
94 (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
Aditya Angadif894b9a2021-03-20 12:15:04 +0530[diff] [blame]95#endif
Aditya Angadid61740b2020-11-19 18:05:33 +0530[diff] [blame]96};
Aditya Angadiccae8a12021-08-09 09:38:58 +0530[diff] [blame]97#endif