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Aditya Angadid61740b2020-11-19 18:05:33 +05301/*
Aditya Angadiccae8a12021-08-09 09:38:58 +05302 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
Aditya Angadid61740b2020-11-19 18:05:33 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Aditya Angadiccae8a12021-08-09 09:38:58 +05307#include <common/debug.h>
Aditya Angadid61740b2020-11-19 18:05:33 +05308#include <plat/arm/common/plat_arm.h>
9#include <platform_def.h>
10
Aditya Angadid61740b2020-11-19 18:05:33 +053011static const arm_tzc_regions_info_t tzc_regions[] = {
12 ARM_TZC_REGIONS_DEF,
13 {}
14};
Aditya Angadiccae8a12021-08-09 09:38:58 +053015
16#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
17static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
18 {
19 /* TZC memory regions for second chip */
20 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
21 {}
22 },
23#if CSS_SGI_CHIP_COUNT > 2
24 {
25 /* TZC memory regions for third chip */
26 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
27 {}
28 },
29#endif
30#if CSS_SGI_CHIP_COUNT > 3
31 {
32 /* TZC memory regions for fourth chip */
33 SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
34 {}
35 },
36#endif
37};
38#endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */
Aditya Angadid61740b2020-11-19 18:05:33 +053039
40/* Initialize the secure environment */
41void plat_arm_security_setup(void)
42{
Aditya Angadiccae8a12021-08-09 09:38:58 +053043 unsigned int i;
Aditya Angadid61740b2020-11-19 18:05:33 +053044
Aditya Angadiccae8a12021-08-09 09:38:58 +053045 INFO("Configuring TrustZone Controller for Chip 0\n");
Aditya Angadid61740b2020-11-19 18:05:33 +053046
Aditya Angadiccae8a12021-08-09 09:38:58 +053047 for (i = 0; i < TZC400_COUNT; i++) {
Aditya Angadid61740b2020-11-19 18:05:33 +053048 arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
Aditya Angadiccae8a12021-08-09 09:38:58 +053049 }
50
51#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
52 unsigned int j;
53
54 for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
55 INFO("Configuring TrustZone Controller for Chip %u\n", i);
Aditya Angadid61740b2020-11-19 18:05:33 +053056
Aditya Angadiccae8a12021-08-09 09:38:58 +053057 for (j = 0; j < TZC400_COUNT; j++) {
58 arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
59 + TZC400_BASE(j), tzc_regions_mc[i-1]);
60 }
61 }
62#endif
Aditya Angadid61740b2020-11-19 18:05:33 +053063}