| Chris Kay | 03be39d | 2021-05-05 13:38:30 +0100 | [diff] [blame] | 1 | Maximum Power Mitigation Mechanism (MPMM) |
| 2 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 3 | |
| 4 | |MPMM| is an optional microarchitectural power management mechanism supported by |
| 5 | some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and |
| 6 | Cortex-A510 cores. This mechanism detects and limits high-activity events to |
| 7 | assist in |SoC| processor power domain dynamic power budgeting and limit the |
| 8 | triggering of whole-rail (i.e. clock chopping) responses to overcurrent |
| 9 | conditions. |
| 10 | |
| Boyan Karatotev | e02c7f3 | 2024-11-25 10:14:26 +0000 | [diff] [blame^] | 11 | |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. |
| Chris Kay | 03be39d | 2021-05-05 13:38:30 +0100 | [diff] [blame] | 12 | |
| 13 | .. warning:: |
| 14 | |
| 15 | |MPMM| exposes gear metrics through the auxiliary |AMU| counters. An |
| 16 | external power controller can use these metrics to budget SoC power by |
| 17 | limiting the number of cores that can execute higher-activity workloads or |
| 18 | switching to a different DVFS operating point. When this is the case, the |
| 19 | |AMU| counters that make up the |MPMM| gears must be enabled by the EL3 |
| 20 | runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for |
| 21 | documentation on enabling auxiliary |AMU| counters. |