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Caesar Wangc1bf6462016-06-21 14:44:01 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Caesar Wangc1bf6462016-06-21 14:44:01 +08005 */
6
Ziyuan Xu4060cfd2017-02-10 11:54:52 +08007#include <cdn_dp.h>
Caesar Wangc1bf6462016-06-21 14:44:01 +08008#include <debug.h>
Isla Mitchelle3631462017-07-14 10:46:32 +01009#include <dfs.h>
Caesar Wangc1bf6462016-06-21 14:44:01 +080010#include <mmio.h>
11#include <plat_sip_calls.h>
12#include <rockchip_sip_svc.h>
13#include <runtime_svc.h>
Caesar Wang9740bba2016-08-25 08:37:42 +080014
Caesar Wang251a34d2016-09-10 06:25:29 +080015#define RK_SIP_DDR_CFG 0x82000008
16#define DRAM_INIT 0x00
17#define DRAM_SET_RATE 0x01
18#define DRAM_ROUND_RATE 0x02
19#define DRAM_SET_AT_SR 0x03
20#define DRAM_GET_BW 0x04
21#define DRAM_GET_RATE 0x05
22#define DRAM_CLR_IRQ 0x06
23#define DRAM_SET_PARAM 0x07
Derek Basehoreff461d02016-10-20 20:46:43 -070024#define DRAM_SET_ODT_PD 0x08
Caesar Wang9740bba2016-08-25 08:37:42 +080025
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080026#define RK_SIP_HDCP_CONTROL 0x82000009
27#define RK_SIP_HDCP_KEY_DATA64 0xC200000A
28
Derek Basehoreff461d02016-10-20 20:46:43 -070029uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
30 uint64_t id, uint64_t arg2)
Caesar Wang9740bba2016-08-25 08:37:42 +080031{
32 switch (id) {
Caesar Wang251a34d2016-09-10 06:25:29 +080033 case DRAM_SET_RATE:
34 return ddr_set_rate((uint32_t)arg0);
35 case DRAM_ROUND_RATE:
36 return ddr_round_rate((uint32_t)arg0);
37 case DRAM_GET_RATE:
Caesar Wang9740bba2016-08-25 08:37:42 +080038 return ddr_get_rate();
Derek Basehoreff461d02016-10-20 20:46:43 -070039 case DRAM_SET_ODT_PD:
40 dram_set_odt_pd(arg0, arg1, arg2);
Caesar Wang9740bba2016-08-25 08:37:42 +080041 break;
42 default:
43 break;
44 }
45
46 return 0;
47}
Caesar Wangc1bf6462016-06-21 14:44:01 +080048
Masahiro Yamada5ac9d962018-04-19 01:18:48 +090049uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
50 u_register_t x1,
51 u_register_t x2,
52 u_register_t x3,
53 u_register_t x4,
54 void *cookie,
55 void *handle,
56 u_register_t flags)
Caesar Wangc1bf6462016-06-21 14:44:01 +080057{
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080058 uint64_t x5, x6;
59
Caesar Wangc1bf6462016-06-21 14:44:01 +080060 switch (smc_fid) {
Caesar Wang251a34d2016-09-10 06:25:29 +080061 case RK_SIP_DDR_CFG:
Derek Basehoreff461d02016-10-20 20:46:43 -070062 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
Ziyuan Xu4060cfd2017-02-10 11:54:52 +080063 case RK_SIP_HDCP_CONTROL:
64 SMC_RET1(handle, dp_hdcp_ctrl(x1));
65 case RK_SIP_HDCP_KEY_DATA64:
66 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5);
67 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6);
68 SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6));
Caesar Wangc1bf6462016-06-21 14:44:01 +080069 default:
70 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
71 SMC_RET1(handle, SMC_UNK);
72 }
73}