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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include <common_def.h>
12#include <tbbr_img_def.h>
13
14/* Special value used to verify platform parameters from BL2 to BL3-1 */
15#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
16
17#define PLATFORM_STACK_SIZE 0x1000
18
Etienne Carriere911de8c2018-02-02 13:23:22 +010019#if ARM_ARCH_MAJOR == 7
20#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
21#define PLATFORM_CLUSTER_COUNT 1
22#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
23#define PLATFORM_CLUSTER1_CORE_COUNT 0
24#else
Jens Wiklander52c798e2015-12-07 14:37:10 +010025#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
26#define PLATFORM_CLUSTER_COUNT 2
27#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
28#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
Etienne Carriere911de8c2018-02-02 13:23:22 +010029#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +010030#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
31 PLATFORM_CLUSTER1_CORE_COUNT)
32
33#define QEMU_PRIMARY_CPU 0
34
35#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
36 PLATFORM_CORE_COUNT)
37#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
38
39#define PLAT_MAX_RET_STATE 1
40#define PLAT_MAX_OFF_STATE 2
41
42/* Local power state for power domains in Run state. */
43#define PLAT_LOCAL_STATE_RUN 0
44/* Local power state for retention. Valid only for CPU power domains */
45#define PLAT_LOCAL_STATE_RET 1
46/*
47 * Local power state for OFF/power-down. Valid for CPU and cluster power
48 * domains.
49 */
50#define PLAT_LOCAL_STATE_OFF 2
51
52/*
53 * Macros used to parse state information from State-ID if it is using the
54 * recommended encoding for State-ID.
55 */
56#define PLAT_LOCAL_PSTATE_WIDTH 4
57#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
58
59/*
60 * Some data must be aligned on the biggest cache line size in the platform.
61 * This is known only to the platform as it might have a combination of
62 * integrated and external caches.
63 */
64#define CACHE_WRITEBACK_SHIFT 6
65#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
66
67/*
68 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM",
69 * and secure DRAM.
70 */
71#define SEC_ROM_BASE 0x00000000
72#define SEC_ROM_SIZE 0x00020000
73
74#define NS_DRAM0_BASE 0x40000000
75#define NS_DRAM0_SIZE 0x3de00000
76
77#define SEC_SRAM_BASE 0x0e000000
Michalis Pappase4c00bb2018-03-20 14:30:00 +080078#define SEC_SRAM_SIZE 0x00060000
Jens Wiklander52c798e2015-12-07 14:37:10 +010079
80#define SEC_DRAM_BASE 0x0e100000
81#define SEC_DRAM_SIZE 0x00f00000
82
Etienne Carriere2ddec182017-10-26 12:05:01 +020083/* Load pageable part of OP-TEE 2MB above secure DRAM base */
84#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000)
Jens Wiklander0acbaaa2017-08-24 13:16:26 +020085#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
86
Jens Wiklander52c798e2015-12-07 14:37:10 +010087/*
88 * ARM-TF lives in SRAM, partition it here
89 */
90
91#define SHARED_RAM_BASE SEC_SRAM_BASE
92#define SHARED_RAM_SIZE 0x00001000
93
94#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
95#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
96#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
97#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \
98 PLAT_QEMU_HOLD_ENTRY_SIZE)
Etienne Carriere5eb85e42017-10-24 01:09:52 +020099#define PLAT_QEMU_HOLD_ENTRY_SHIFT 3
100#define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100101#define PLAT_QEMU_HOLD_STATE_WAIT 0
102#define PLAT_QEMU_HOLD_STATE_GO 1
103
104#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE)
105#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
106
107/*
108 * BL1 specific defines.
109 *
110 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
111 * addresses.
112 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
113 * the current BL1 RW debug size plus a little space for growth.
114 */
115#define BL1_RO_BASE SEC_ROM_BASE
116#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
117#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
118#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
119
120/*
121 * BL2 specific defines.
122 *
123 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
124 * size plus a little space for growth.
125 */
Michalis Pappase4c00bb2018-03-20 14:30:00 +0800126#define BL2_BASE (BL31_BASE - 0x25000)
Jens Wiklander52c798e2015-12-07 14:37:10 +0100127#define BL2_LIMIT BL31_BASE
128
129/*
130 * BL3-1 specific defines.
131 *
132 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
133 * current BL3-1 debug size plus a little space for growth.
134 */
135#define BL31_BASE (BL31_LIMIT - 0x20000)
136#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
137#define BL31_PROGBITS_LIMIT BL1_RW_BASE
138
139
140/*
141 * BL3-2 specific defines.
142 *
143 * BL3-2 can execute from Secure SRAM, or Secure DRAM.
144 */
145#define BL32_SRAM_BASE BL_RAM_BASE
146#define BL32_SRAM_LIMIT BL31_BASE
147#define BL32_DRAM_BASE SEC_DRAM_BASE
148#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
149
150#define SEC_SRAM_ID 0
151#define SEC_DRAM_ID 1
152
153#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID
154# define BL32_MEM_BASE BL_RAM_BASE
155# define BL32_MEM_SIZE BL_RAM_SIZE
156# define BL32_BASE BL32_SRAM_BASE
157# define BL32_LIMIT BL32_SRAM_LIMIT
158#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID
159# define BL32_MEM_BASE SEC_DRAM_BASE
160# define BL32_MEM_SIZE SEC_DRAM_SIZE
161# define BL32_BASE BL32_DRAM_BASE
162# define BL32_LIMIT BL32_DRAM_LIMIT
163#else
164# error "Unsupported BL32_RAM_LOCATION_ID value"
165#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +0100166
167#define NS_IMAGE_OFFSET 0x60000000
168
David Cunadoc1503122018-02-16 21:12:58 +0000169#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
170#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
Michalis Pappasba861122018-02-28 14:36:03 +0800171#define MAX_MMAP_REGIONS 10
Jens Wiklander52c798e2015-12-07 14:37:10 +0100172#define MAX_XLAT_TABLES 6
173#define MAX_IO_DEVICES 3
174#define MAX_IO_HANDLES 4
175
176/*
177 * PL011 related constants
178 */
179#define UART0_BASE 0x09000000
180#define UART1_BASE 0x09040000
181#define UART0_CLK_IN_HZ 1
182#define UART1_CLK_IN_HZ 1
183
184#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
185#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
186
187#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE
188#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ
189
190#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
191
192#define QEMU_FLASH0_BASE 0x04000000
193#define QEMU_FLASH0_SIZE 0x04000000
194
195#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
196#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
197
198#define DEVICE0_BASE 0x08000000
199#define DEVICE0_SIZE 0x00021000
200#define DEVICE1_BASE 0x09000000
Michalis Pappas8e235152018-03-03 18:26:11 +0800201#define DEVICE1_SIZE 0x00041000
Jens Wiklander52c798e2015-12-07 14:37:10 +0100202
203/*
204 * GIC related constants
205 */
206
207#define GICD_BASE 0x8000000
208#define GICC_BASE 0x8010000
209#define GICR_BASE 0
210
211
212#define QEMU_IRQ_SEC_SGI_0 8
213#define QEMU_IRQ_SEC_SGI_1 9
214#define QEMU_IRQ_SEC_SGI_2 10
215#define QEMU_IRQ_SEC_SGI_3 11
216#define QEMU_IRQ_SEC_SGI_4 12
217#define QEMU_IRQ_SEC_SGI_5 13
218#define QEMU_IRQ_SEC_SGI_6 14
219#define QEMU_IRQ_SEC_SGI_7 15
220
221/*
222 * DT related constants
223 */
224#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE
225#define PLAT_QEMU_DT_MAX_SIZE 0x10000
226
227/*
228 * System counter
229 */
230#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
231
232#endif /* __PLATFORM_DEF_H__ */