blob: 3986153a284c76d77aabcff3798b0ca13c628b41 [file] [log] [blame]
Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <mmio.h>
8#include <debug.h>
9#include <endian.h>
10#include "platform_def.h"
11#include "soc.h"
12
13/*
14 * Get GIC offset
15 * For LS1043a rev1.0, GIC base address align with 4k.
16 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
17 * is set, GIC base address align with 4K, or else align
18 * with 64k.
19 */
20void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
21{
22
23 uint32_t *ccsr_svr = (uint32_t *)DCFG_CCSR_SVR;
24 uint32_t *gic_align = (uint32_t *)SCFG_GIC400_ALIGN;
25 uint32_t val;
26 uint32_t soc_dev_id;
27
28 val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
29 soc_dev_id = val & (SVR_WO_E << 8);
30
31 if ((soc_dev_id == (SVR_LS1043A << 8) ||
32 soc_dev_id == (SVR_LS1043AE << 8)) &&
33 ((val & 0xff) == REV1_1)) {
34 val = be32toh(mmio_read_32((uintptr_t)gic_align));
35 if (val & (1 << GIC_ADDR_BIT)) {
36 *gicc_base = GICC_BASE;
37 *gicd_base = GICD_BASE;
38 } else {
39 *gicc_base = GICC_BASE_64K;
40 *gicd_base = GICD_BASE_64K;
41 }
42 } else {
43 *gicc_base = GICC_BASE;
44 *gicd_base = GICD_BASE;
45 }
46}