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Soby Mathew12012dd2015-10-26 14:01:53 +00001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathew12012dd2015-10-26 14:01:53 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew12012dd2015-10-26 14:01:53 +00005 */
6#include <assert.h>
7#include <gic_common.h>
8#include <gicv2.h>
9#include <interrupt_mgmt.h>
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010010#include <platform.h>
Soby Mathew12012dd2015-10-26 14:01:53 +000011
12/*
13 * The following platform GIC functions are weakly defined. They
14 * provide typical implementations that may be re-used by multiple
15 * platforms but may also be overridden by a platform if required.
16 */
17#pragma weak plat_ic_get_pending_interrupt_id
18#pragma weak plat_ic_get_pending_interrupt_type
19#pragma weak plat_ic_acknowledge_interrupt
20#pragma weak plat_ic_get_interrupt_type
21#pragma weak plat_ic_end_of_interrupt
22#pragma weak plat_interrupt_type_to_line
23
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010024#pragma weak plat_ic_get_running_priority
Jeenu Viswambharan522a4652017-09-22 08:32:09 +010025#pragma weak plat_ic_is_spi
26#pragma weak plat_ic_is_ppi
27#pragma weak plat_ic_is_sgi
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010028#pragma weak plat_ic_get_interrupt_active
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010029#pragma weak plat_ic_enable_interrupt
30#pragma weak plat_ic_disable_interrupt
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +010031#pragma weak plat_ic_set_interrupt_priority
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010032#pragma weak plat_ic_set_interrupt_type
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010033#pragma weak plat_ic_raise_el3_sgi
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010034#pragma weak plat_ic_set_spi_routing
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +010035
Soby Mathew12012dd2015-10-26 14:01:53 +000036/*
37 * This function returns the highest priority pending interrupt at
38 * the Interrupt controller
39 */
40uint32_t plat_ic_get_pending_interrupt_id(void)
41{
42 unsigned int id;
43
44 id = gicv2_get_pending_interrupt_id();
45 if (id == GIC_SPURIOUS_INTERRUPT)
46 return INTR_ID_UNAVAILABLE;
47
48 return id;
49}
50
51/*
52 * This function returns the type of the highest priority pending interrupt
53 * at the Interrupt controller. In the case of GICv2, the Highest Priority
54 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of
55 * the pending interrupt. The type of interrupt depends upon the id value
56 * as follows.
57 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt
58 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt.
59 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
60 * type.
61 */
62uint32_t plat_ic_get_pending_interrupt_type(void)
63{
64 unsigned int id;
65
66 id = gicv2_get_pending_interrupt_type();
67
68 /* Assume that all secure interrupts are S-EL1 interrupts */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010069 if (id < PENDING_G1_INTID) {
70#if GICV2_G0_FOR_EL3
71 return INTR_TYPE_EL3;
72#else
Soby Mathew12012dd2015-10-26 14:01:53 +000073 return INTR_TYPE_S_EL1;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010074#endif
75 }
Soby Mathew12012dd2015-10-26 14:01:53 +000076
77 if (id == GIC_SPURIOUS_INTERRUPT)
78 return INTR_TYPE_INVAL;
79
80 return INTR_TYPE_NS;
81}
82
83/*
84 * This function returns the highest priority pending interrupt at
85 * the Interrupt controller and indicates to the Interrupt controller
86 * that the interrupt processing has started.
87 */
88uint32_t plat_ic_acknowledge_interrupt(void)
89{
90 return gicv2_acknowledge_interrupt();
91}
92
93/*
94 * This function returns the type of the interrupt `id`, depending on how
95 * the interrupt has been configured in the interrupt controller
96 */
97uint32_t plat_ic_get_interrupt_type(uint32_t id)
98{
99 unsigned int type;
100
101 type = gicv2_get_interrupt_group(id);
102
103 /* Assume that all secure interrupts are S-EL1 interrupts */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100104 return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS :
105#if GICV2_G0_FOR_EL3
106 INTR_TYPE_EL3;
107#else
108 INTR_TYPE_S_EL1;
109#endif
Soby Mathew12012dd2015-10-26 14:01:53 +0000110}
111
112/*
113 * This functions is used to indicate to the interrupt controller that
114 * the processing of the interrupt corresponding to the `id` has
115 * finished.
116 */
117void plat_ic_end_of_interrupt(uint32_t id)
118{
119 gicv2_end_of_interrupt(id);
120}
121
122/*
123 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
124 * The interrupt controller knows which pin/line it uses to signal a type of
125 * interrupt. It lets the interrupt management framework determine
126 * for a type of interrupt and security state, which line should be used in the
127 * SCR_EL3 to control its routing to EL3. The interrupt line is represented
128 * as the bit position of the IRQ or FIQ bit in the SCR_EL3.
129 */
130uint32_t plat_interrupt_type_to_line(uint32_t type,
131 uint32_t security_state)
132{
133 assert(type == INTR_TYPE_S_EL1 ||
134 type == INTR_TYPE_EL3 ||
135 type == INTR_TYPE_NS);
136
Santeri Salko4ed23382018-02-08 22:01:26 +0200137 assert(sec_state_is_valid(security_state));
138
Soby Mathew12012dd2015-10-26 14:01:53 +0000139 /* Non-secure interrupts are signaled on the IRQ line always */
140 if (type == INTR_TYPE_NS)
141 return __builtin_ctz(SCR_IRQ_BIT);
142
143 /*
144 * Secure interrupts are signaled using the IRQ line if the FIQ is
145 * not enabled else they are signaled using the FIQ line.
146 */
147 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) :
148 __builtin_ctz(SCR_IRQ_BIT));
149}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100150
151unsigned int plat_ic_get_running_priority(void)
152{
153 return gicv2_get_running_priority();
154}
Jeenu Viswambharan522a4652017-09-22 08:32:09 +0100155
156int plat_ic_is_spi(unsigned int id)
157{
158 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID);
159}
160
161int plat_ic_is_ppi(unsigned int id)
162{
163 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID);
164}
165
166int plat_ic_is_sgi(unsigned int id)
167{
168 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID);
169}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100170
171unsigned int plat_ic_get_interrupt_active(unsigned int id)
172{
173 return gicv2_get_interrupt_active(id);
174}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100175
176void plat_ic_enable_interrupt(unsigned int id)
177{
178 gicv2_enable_interrupt(id);
179}
180
181void plat_ic_disable_interrupt(unsigned int id)
182{
183 gicv2_disable_interrupt(id);
184}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100185
186void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority)
187{
188 gicv2_set_interrupt_priority(id, priority);
189}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100190
191int plat_ic_has_interrupt_type(unsigned int type)
192{
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000193 int has_interrupt_type = 0;
194
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100195 switch (type) {
196#if GICV2_G0_FOR_EL3
197 case INTR_TYPE_EL3:
198#else
199 case INTR_TYPE_S_EL1:
200#endif
201 case INTR_TYPE_NS:
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000202 has_interrupt_type = 1;
203 break;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100204 default:
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000205 /* Do nothing in default case */
206 break;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100207 }
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000208
209 return has_interrupt_type;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100210}
211
212void plat_ic_set_interrupt_type(unsigned int id, unsigned int type)
213{
214 int gicv2_type = 0;
215
216 /* Map canonical interrupt type to GICv2 type */
217 switch (type) {
218#if GICV2_G0_FOR_EL3
219 case INTR_TYPE_EL3:
220#else
221 case INTR_TYPE_S_EL1:
222#endif
223 gicv2_type = GICV2_INTR_GROUP0;
224 break;
225 case INTR_TYPE_NS:
226 gicv2_type = GICV2_INTR_GROUP1;
227 break;
228 default:
229 assert(0);
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000230 break;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100231 }
232
233 gicv2_set_interrupt_type(id, gicv2_type);
234}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100235
236void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
237{
238#if GICV2_G0_FOR_EL3
239 int id;
240
241 /* Target must be a valid MPIDR in the system */
242 id = plat_core_pos_by_mpidr(target);
243 assert(id >= 0);
244
245 /* Verify that this is a secure SGI */
246 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3);
247
248 gicv2_raise_sgi(sgi_num, id);
249#else
250 assert(0);
251#endif
252}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100253
254void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode,
255 u_register_t mpidr)
256{
257 int proc_num = 0;
258
259 switch (routing_mode) {
260 case INTR_ROUTING_MODE_PE:
261 proc_num = plat_core_pos_by_mpidr(mpidr);
262 assert(proc_num >= 0);
263 break;
264 case INTR_ROUTING_MODE_ANY:
265 /* Bit mask selecting all 8 CPUs as candidates */
266 proc_num = -1;
267 break;
268 default:
269 assert(0);
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000270 break;
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100271 }
272
273 gicv2_set_spi_routing(id, proc_num);
274}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100275
276void plat_ic_set_interrupt_pending(unsigned int id)
277{
278 gicv2_set_interrupt_pending(id);
279}
280
281void plat_ic_clear_interrupt_pending(unsigned int id)
282{
283 gicv2_clear_interrupt_pending(id);
284}
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100285
286unsigned int plat_ic_set_priority_mask(unsigned int mask)
287{
288 return gicv2_set_pmr(mask);
289}
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100290
291unsigned int plat_ic_get_interrupt_id(unsigned int raw)
292{
293 unsigned int id = (raw & INT_ID_MASK);
294
295 if (id == GIC_SPURIOUS_INTERRUPT)
296 id = INTR_ID_UNAVAILABLE;
297
298 return id;
299}