blob: 19bd76f800de1adaa53d40e837176d1af3c3ea03 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Roberto Vargas2b36b152018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <board_css_def.h>
8#include <mmio.h>
Vikram Kanigiriaf2bc5f2015-08-03 23:58:19 +01009#include <nic_400.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <platform_def.h>
Roberto Vargas2b36b152018-02-12 12:36:17 +000011#include <soc_css.h>
Dan Handley9df48042015-03-19 18:58:55 +000012#include <soc_css_def.h>
13
Dan Handley9df48042015-03-19 18:58:55 +000014void soc_css_init_nic400(void)
15{
16 /*
17 * NIC-400 Access Control Initialization
18 *
19 * Define access privileges by setting each corresponding bit to:
20 * 0 = Secure access only
21 * 1 = Non-secure access allowed
22 */
23
24 /*
25 * Allow non-secure access to some SOC regions, excluding UART1, which
26 * remains secure.
27 * Note: This is the NIC-400 device on the SOC
28 */
29 mmio_write_32(SOC_CSS_NIC400_BASE +
30 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0);
31 mmio_write_32(SOC_CSS_NIC400_BASE +
32 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0);
33 mmio_write_32(SOC_CSS_NIC400_BASE +
34 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0);
35 mmio_write_32(SOC_CSS_NIC400_BASE +
36 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
37 mmio_write_32(SOC_CSS_NIC400_BASE +
38 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
39 mmio_write_32(SOC_CSS_NIC400_BASE +
40 NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
41 ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
42
Dan Handley9df48042015-03-19 18:58:55 +000043}
44
45
46#define PCIE_SECURE_REG 0x3000
47/* Mask uses REG and MEM access bits */
48#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1))
49
50void soc_css_init_pcie(void)
51{
52#if !PLAT_juno
53 /*
54 * Do not initialize PCIe in emulator environment.
55 * Platform ID register not supported on Juno
56 */
57 if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) ==
58 BOARD_CSS_PLAT_TYPE_EMULATOR)
59 return;
60#endif /* PLAT_juno */
61
62 /*
63 * PCIE Root Complex Security settings to enable non-secure
64 * access to config registers.
65 */
66 mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
67 PCIE_SEC_ACCESS_MASK);
68}