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git01.mediatek.com / filogic / atf / dfa4cf456db3489615772407d5e208941b23025c / . / include / lib / cpus / aarch64 / cortex_x3.h
blob: 5429078779ffbd9178ec0f0cfa0918cc1b1c9ce3 [file] [log] [blame]
Boyan Karatotevbdf953c2022-10-25 11:29:04 +0100[diff] [blame]1/*
Bipin Ravidfa4cf42023-12-20 14:53:37 -0600[diff] [blame^]2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
Boyan Karatotevbdf953c2022-10-25 11:29:04 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_X3_H
8#define CORTEX_X3_H
9
10#define CORTEX_X3_MIDR U(0x410FD4E0)
11
12/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
Harrison Mutai82dd5ac2022-11-11 14:09:55 +0000[diff] [blame]13#define CORTEX_X3_BHB_LOOP_COUNT U(132)
Boyan Karatotevbdf953c2022-10-25 11:29:04 +0100[diff] [blame]14
15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
18#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
Harrison Mutai82dd5ac2022-11-11 14:09:55 +0000[diff] [blame]23#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
25#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
26#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
Boyan Karatotevbdf953c2022-10-25 11:29:04 +0100[diff] [blame]27
Boyan Karatotev6559dbd2022-10-03 14:18:28 +0100[diff] [blame]28/*******************************************************************************
Bipin Ravidfa4cf42023-12-20 14:53:37 -0600[diff] [blame^]29 * CPU Auxiliary Control register specific definitions.
30 ******************************************************************************/
31#define CORTEX_X3_CPUACTLR_EL1 S3_0_C15_C1_0
32
33/*******************************************************************************
Boyan Karatotev6559dbd2022-10-03 14:18:28 +0100[diff] [blame]34 * CPU Auxiliary Control register 2 specific definitions.
35 ******************************************************************************/
36#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
37#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
38
Sona Mathew95168582023-09-05 14:10:03 -0500[diff] [blame]39/*******************************************************************************
40 * CPU Auxiliary Control register 5 specific definitions.
41 ******************************************************************************/
42#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
43#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
44#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
45
Sona Mathew35c7d392023-10-03 17:09:09 -0500[diff] [blame]46/*******************************************************************************
47 * CPU Extended Control register 2 specific definitions.
48 ******************************************************************************/
49#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5
50
51#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11)
52#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
53#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
54
Sona Mathew2eab9d02023-11-06 13:48:22 -0600[diff] [blame]55/*******************************************************************************
56 * CPU Auxiliary Control register 3 specific definitions.
57 ******************************************************************************/
58#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2
59#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
60
Boyan Karatotevbdf953c2022-10-25 11:29:04 +0100[diff] [blame]61#endif /* CORTEX_X3_H */