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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_H__
32#define __PLATFORM_H__
33
34#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010035
36
37/*******************************************************************************
38 * Platform binary types for linking
39 ******************************************************************************/
40#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
41#define PLATFORM_LINKER_ARCH aarch64
42
43/*******************************************************************************
44 * Generic platform constants
45 ******************************************************************************/
Andrew Thoelke65668f92014-03-20 10:48:23 +000046
47/* Size of cacheable stacks */
48#define PLATFORM_STACK_SIZE 0x800
49
50/* Size of coherent stacks for debug and release builds */
51#if DEBUG
52#define PCPU_DV_MEM_STACK_SIZE 0x400
53#else
54#define PCPU_DV_MEM_STACK_SIZE 0x300
55#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010056
57#define FIRMWARE_WELCOME_STR "Booting trusted firmware boot loader stage 1\n\r"
Harry Liebel561cd332014-02-14 14:42:48 +000058
59/* Trusted Boot Firmware BL2 */
Achin Gupta4f6ad662013-10-25 09:08:21 +010060#define BL2_IMAGE_NAME "bl2.bin"
Achin Guptae4d084e2014-02-19 17:18:23 +000061
Harry Liebel561cd332014-02-14 14:42:48 +000062/* EL3 Runtime Firmware BL31 */
Achin Guptae4d084e2014-02-19 17:18:23 +000063#define BL31_IMAGE_NAME "bl31.bin"
64
Harry Liebel561cd332014-02-14 14:42:48 +000065/* Secure Payload BL32 (Trusted OS) */
Achin Guptae4d084e2014-02-19 17:18:23 +000066#define BL32_IMAGE_NAME "bl32.bin"
67
Harry Liebel561cd332014-02-14 14:42:48 +000068/* Non-Trusted Firmware BL33 and its load address */
Achin Guptae4d084e2014-02-19 17:18:23 +000069#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
70#define NS_IMAGE_OFFSET (DRAM_BASE + 0x8000000) /* DRAM + 128MB */
71
Harry Liebel561cd332014-02-14 14:42:48 +000072/* Firmware Image Package */
73#define FIP_IMAGE_NAME "fip.bin"
74
Achin Gupta4f6ad662013-10-25 09:08:21 +010075#define PLATFORM_CACHE_LINE_SIZE 64
76#define PLATFORM_CLUSTER_COUNT 2ull
77#define PLATFORM_CLUSTER0_CORE_COUNT 4
78#define PLATFORM_CLUSTER1_CORE_COUNT 4
Ian Spray84687392014-01-02 16:57:12 +000079#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
80 PLATFORM_CLUSTER0_CORE_COUNT)
Achin Gupta4f6ad662013-10-25 09:08:21 +010081#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
82#define PRIMARY_CPU 0x0
Harry Liebel561cd332014-02-14 14:42:48 +000083#define MAX_IO_DEVICES 3
James Morrisseyf2f9bb52014-02-10 16:18:59 +000084#define MAX_IO_HANDLES 4
Achin Gupta4f6ad662013-10-25 09:08:21 +010085
86/* Constants for accessing platform configuration */
87#define CONFIG_GICD_ADDR 0
88#define CONFIG_GICC_ADDR 1
89#define CONFIG_GICH_ADDR 2
90#define CONFIG_GICV_ADDR 3
91#define CONFIG_MAX_AFF0 4
92#define CONFIG_MAX_AFF1 5
93/* Indicate whether the CPUECTLR SMP bit should be enabled. */
94#define CONFIG_CPU_SETUP 6
95#define CONFIG_BASE_MMAP 7
Harry Liebel30affd52013-10-30 17:41:48 +000096/* Indicates whether CCI should be enabled on the platform. */
97#define CONFIG_HAS_CCI 8
Harry Liebelcef93392014-04-01 19:27:38 +010098#define CONFIG_HAS_TZC 9
99#define CONFIG_LIMIT 10
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100
101/*******************************************************************************
102 * Platform memory map related constants
103 ******************************************************************************/
104#define TZROM_BASE 0x00000000
105#define TZROM_SIZE 0x04000000
106
107#define TZRAM_BASE 0x04000000
108#define TZRAM_SIZE 0x40000
109
110#define FLASH0_BASE 0x08000000
111#define FLASH0_SIZE TZROM_SIZE
112
113#define FLASH1_BASE 0x0c000000
114#define FLASH1_SIZE 0x04000000
115
116#define PSRAM_BASE 0x14000000
117#define PSRAM_SIZE 0x04000000
118
119#define VRAM_BASE 0x18000000
120#define VRAM_SIZE 0x02000000
121
122/* Aggregate of all devices in the first GB */
123#define DEVICE0_BASE 0x1a000000
124#define DEVICE0_SIZE 0x12200000
125
126#define DEVICE1_BASE 0x2f000000
127#define DEVICE1_SIZE 0x200000
128
129#define NSRAM_BASE 0x2e000000
130#define NSRAM_SIZE 0x10000
131
132/* Location of trusted dram on the base fvp */
133#define TZDRAM_BASE 0x06000000
134#define TZDRAM_SIZE 0x02000000
135#define MBOX_OFF 0x1000
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136
137#define DRAM_BASE 0x80000000ull
138#define DRAM_SIZE 0x80000000ull
139
140#define PCIE_EXP_BASE 0x40000000
141#define TZRNG_BASE 0x7fe60000
142#define TZNVCTR_BASE 0x7fe70000
143#define TZROOTKEY_BASE 0x7fe80000
144
145/* Memory mapped Generic timer interfaces */
146#define SYS_CNTCTL_BASE 0x2a430000
147#define SYS_CNTREAD_BASE 0x2a800000
148#define SYS_TIMCTL_BASE 0x2a810000
149
150/* Counter timer module offsets */
151#define CNTNSAR 0x4
152#define CNTNSAR_NS_SHIFT(x) x
153
154#define CNTACR_BASE(x) (0x40 + (x << 2))
155#define CNTACR_RPCT_SHIFT 0x0
156#define CNTACR_RVCT_SHIFT 0x1
157#define CNTACR_RFRQ_SHIFT 0x2
158#define CNTACR_RVOFF_SHIFT 0x3
159#define CNTACR_RWVT_SHIFT 0x4
160#define CNTACR_RWPT_SHIFT 0x5
161
162/* V2M motherboard system registers & offsets */
163#define VE_SYSREGS_BASE 0x1c010000
164#define V2M_SYS_ID 0x0
165#define V2M_SYS_LED 0x8
166#define V2M_SYS_CFGDATA 0xa0
167#define V2M_SYS_CFGCTRL 0xa4
168
169/*
170 * V2M sysled bit definitions. The values written to this
171 * register are defined in arch.h & runtime_svc.h. Only
172 * used by the primary cpu to diagnose any cold boot issues.
173 *
174 * SYS_LED[0] - Security state (S=0/NS=1)
175 * SYS_LED[2:1] - Exception Level (EL3-EL0)
176 * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
177 *
178 */
179#define SYS_LED_SS_SHIFT 0x0
180#define SYS_LED_EL_SHIFT 0x1
181#define SYS_LED_EC_SHIFT 0x3
182
183#define SYS_LED_SS_MASK 0x1
184#define SYS_LED_EL_MASK 0x3
185#define SYS_LED_EC_MASK 0x1f
186
187/* V2M sysid register bits */
188#define SYS_ID_REV_SHIFT 27
189#define SYS_ID_HBI_SHIFT 16
190#define SYS_ID_BLD_SHIFT 12
191#define SYS_ID_ARCH_SHIFT 8
192#define SYS_ID_FPGA_SHIFT 0
193
194#define SYS_ID_REV_MASK 0xf
195#define SYS_ID_HBI_MASK 0xfff
196#define SYS_ID_BLD_MASK 0xf
197#define SYS_ID_ARCH_MASK 0xf
198#define SYS_ID_FPGA_MASK 0xff
199
200#define SYS_ID_BLD_LENGTH 4
201
202#define REV_FVP 0x0
203#define HBI_FVP_BASE 0x020
204#define HBI_FOUNDATION 0x010
205
206#define BLD_GIC_VE_MMAP 0x0
207#define BLD_GIC_A53A57_MMAP 0x1
208
209#define ARCH_MODEL 0x1
210
211/* FVP Power controller base address*/
212#define PWRC_BASE 0x1c100000
213
214/*******************************************************************************
215 * Platform specific per affinity states. Distinction between off and suspend
216 * is made to allow reporting of a suspended cpu as still being on e.g. in the
217 * affinity_info psci call.
218 ******************************************************************************/
219#define PLATFORM_MAX_AFF0 4
220#define PLATFORM_MAX_AFF1 2
221#define PLAT_AFF_UNK 0xff
222
223#define PLAT_AFF0_OFF 0x0
224#define PLAT_AFF0_ONPENDING 0x1
225#define PLAT_AFF0_SUSPEND 0x2
226#define PLAT_AFF0_ON 0x3
227
228#define PLAT_AFF1_OFF 0x0
229#define PLAT_AFF1_ONPENDING 0x1
230#define PLAT_AFF1_SUSPEND 0x2
231#define PLAT_AFF1_ON 0x3
232
233/*******************************************************************************
234 * BL2 specific defines.
235 ******************************************************************************/
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000236#define BL2_BASE 0x0402D000
Achin Gupta4f6ad662013-10-25 09:08:21 +0100237
238/*******************************************************************************
239 * BL31 specific defines.
240 ******************************************************************************/
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000241#define BL31_BASE 0x0400C000
Achin Gupta4f6ad662013-10-25 09:08:21 +0100242
243/*******************************************************************************
Achin Guptaa3050ed2014-02-19 17:52:35 +0000244 * BL32 specific defines.
245 ******************************************************************************/
246#define BL32_BASE (TZDRAM_BASE + 0x2000)
247
248/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249 * Platform specific page table and MMU setup constants
250 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251#define ADDR_SPACE_SIZE (1ull << 32)
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000252#define MAX_XLAT_TABLES 3
253#define MAX_MMAP_REGIONS 16
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255
256/*******************************************************************************
257 * CCI-400 related constants
258 ******************************************************************************/
259#define CCI400_BASE 0x2c090000
260#define CCI400_SL_IFACE_CLUSTER0 3
261#define CCI400_SL_IFACE_CLUSTER1 4
262#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
263 CCI400_SL_IFACE_CLUSTER1 : \
264 CCI400_SL_IFACE_CLUSTER0)
265
266/*******************************************************************************
267 * GIC-400 & interrupt handling related constants
268 ******************************************************************************/
269/* VE compatible GIC memory map */
270#define VE_GICD_BASE 0x2c001000
271#define VE_GICC_BASE 0x2c002000
272#define VE_GICH_BASE 0x2c004000
273#define VE_GICV_BASE 0x2c006000
274
275/* Base FVP compatible GIC memory map */
276#define BASE_GICD_BASE 0x2f000000
277#define BASE_GICR_BASE 0x2f100000
278#define BASE_GICC_BASE 0x2c000000
279#define BASE_GICH_BASE 0x2c010000
280#define BASE_GICV_BASE 0x2c02f000
281
282#define IRQ_TZ_WDOG 56
283#define IRQ_SEC_PHY_TIMER 29
284#define IRQ_SEC_SGI_0 8
285#define IRQ_SEC_SGI_1 9
286#define IRQ_SEC_SGI_2 10
287#define IRQ_SEC_SGI_3 11
288#define IRQ_SEC_SGI_4 12
289#define IRQ_SEC_SGI_5 13
290#define IRQ_SEC_SGI_6 14
291#define IRQ_SEC_SGI_7 15
292#define IRQ_SEC_SGI_8 16
293
294/*******************************************************************************
295 * PL011 related constants
296 ******************************************************************************/
Achin Gupta8aa0cd42014-02-09 13:47:08 +0000297#define PL011_UART0_BASE 0x1c090000
298#define PL011_UART1_BASE 0x1c0a0000
299#define PL011_UART2_BASE 0x1c0b0000
300#define PL011_UART3_BASE 0x1c0c0000
Achin Gupta4f6ad662013-10-25 09:08:21 +0100301
Harry Liebelcef93392014-04-01 19:27:38 +0100302
303/*******************************************************************************
304 * TrustZone address space controller related constants
305 ******************************************************************************/
306#define TZC400_BASE 0x2a4a0000
307
308/*
309 * The NSAIDs for this platform as used to program the TZC400.
310 * TODO:
311 * This list and the numbers in it is still changing on the Base FVP.
312 * For now only specify the NSAIDs we actually use.
313 */
314
315/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
316#define FVP_AID_WIDTH 4
317#define FVP_NSAID_DEFAULT 0
318#define FVP_NSAID_AP 9 /* Application Processors */
319
320/* FIXME: Currently incorrectly used by Virtio */
321#define FVP_NSAID_RES5 15
322
323
Achin Gupta4f6ad662013-10-25 09:08:21 +0100324/*******************************************************************************
325 * Declarations and constants to access the mailboxes safely. Each mailbox is
326 * aligned on the biggest cache line size in the platform. This is known only
327 * to the platform as it might have a combination of integrated and external
328 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
329 * line at any cache level. They could belong to different cpus/clusters &
330 * get written while being protected by different locks causing corruption of
331 * a valid mailbox address.
332 ******************************************************************************/
333#define CACHE_WRITEBACK_SHIFT 6
334#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
335
336#ifndef __ASSEMBLY__
337
Dan Handley2bd4ef22014-04-09 13:14:54 +0100338#include <stdint.h>
339
340
Dan Handleye2712bc2014-04-10 15:37:22 +0100341typedef volatile struct mailbox {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342 unsigned long value
343 __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
Dan Handleye2712bc2014-04-10 15:37:22 +0100344} mailbox_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100345
346/*******************************************************************************
Dan Handley2bd4ef22014-04-09 13:14:54 +0100347 * Forward declarations
348 ******************************************************************************/
349struct plat_pm_ops;
350struct meminfo;
Dan Handley2bd4ef22014-04-09 13:14:54 +0100351
352/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100353 * Function and variable prototypes
354 ******************************************************************************/
355extern unsigned long *bl1_normal_ram_base;
356extern unsigned long *bl1_normal_ram_len;
357extern unsigned long *bl1_normal_ram_limit;
358extern unsigned long *bl1_normal_ram_zi_base;
359extern unsigned long *bl1_normal_ram_zi_len;
360
361extern unsigned long *bl1_coherent_ram_base;
362extern unsigned long *bl1_coherent_ram_len;
363extern unsigned long *bl1_coherent_ram_limit;
364extern unsigned long *bl1_coherent_ram_zi_base;
365extern unsigned long *bl1_coherent_ram_zi_len;
366extern unsigned long warm_boot_entrypoint;
367
368extern void bl1_plat_arch_setup(void);
369extern void bl2_plat_arch_setup(void);
370extern void bl31_plat_arch_setup(void);
Dan Handleya4cb68e2014-04-23 13:47:06 +0100371extern int platform_setup_pm(const struct plat_pm_ops **);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100372extern unsigned int platform_get_core_pos(unsigned long mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100373extern void enable_mmu(void);
Dan Handley2bd4ef22014-04-09 13:14:54 +0100374extern void configure_mmu(struct meminfo *,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100375 unsigned long,
376 unsigned long,
377 unsigned long,
378 unsigned long);
379extern unsigned long platform_get_cfgvar(unsigned int);
380extern int platform_config_setup(void);
381extern void plat_report_exception(unsigned long);
382extern unsigned long plat_get_ns_image_entrypoint(void);
Achin Guptac8afc782013-11-25 18:45:02 +0000383extern unsigned long platform_get_stack(unsigned long mpidr);
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100384extern uint64_t plat_get_syscnt_freq(void);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100385
Ian Spray84687392014-01-02 16:57:12 +0000386/* Declarations for fvp_gic.c */
387extern void gic_cpuif_deactivate(unsigned int);
388extern void gic_cpuif_setup(unsigned int);
389extern void gic_pcpu_distif_setup(unsigned int);
390extern void gic_setup(void);
391
Achin Gupta4f6ad662013-10-25 09:08:21 +0100392/* Declarations for fvp_topology.c */
393extern int plat_setup_topology(void);
394extern int plat_get_max_afflvl(void);
395extern unsigned int plat_get_aff_count(unsigned int, unsigned long);
396extern unsigned int plat_get_aff_state(unsigned int, unsigned long);
397
James Morrissey9d72b4e2014-02-10 17:04:32 +0000398/* Declarations for plat_io_storage.c */
399extern void io_setup(void);
400extern int plat_get_image_source(const char *image_name,
Dan Handleya4cb68e2014-04-23 13:47:06 +0100401 uintptr_t *dev_handle, uintptr_t *image_spec);
James Morrissey9d72b4e2014-02-10 17:04:32 +0000402
Harry Liebelcef93392014-04-01 19:27:38 +0100403/* Declarations for plat_security.c */
404extern void plat_security_setup(void);
405
406
Achin Gupta4f6ad662013-10-25 09:08:21 +0100407#endif /*__ASSEMBLY__*/
408
409#endif /* __PLATFORM_H__ */