Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <stdio.h> |
| 32 | #include <string.h> |
| 33 | #include <assert.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include <console.h> |
| 36 | #include <platform.h> |
| 37 | #include <psci.h> |
| 38 | #include <psci_private.h> |
Achin Gupta | c8afc78 | 2013-11-25 18:45:02 +0000 | [diff] [blame] | 39 | #include <runtime_svc.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
| 42 | * Arrays that contains information needs to resume a cpu's execution when woken |
| 43 | * out of suspend or off states. 'psci_ns_einfo_idx' keeps track of the next |
Achin Gupta | a59caa4 | 2013-12-05 14:21:04 +0000 | [diff] [blame] | 44 | * free index in the 'psci_ns_entry_info' & 'psci_suspend_context' arrays. Each |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 45 | * cpu is allocated a single entry in each array during startup. |
| 46 | ******************************************************************************/ |
Achin Gupta | a59caa4 | 2013-12-05 14:21:04 +0000 | [diff] [blame] | 47 | suspend_context psci_suspend_context[PSCI_NUM_AFFS]; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | ns_entry_info psci_ns_entry_info[PSCI_NUM_AFFS]; |
| 49 | unsigned int psci_ns_einfo_idx; |
| 50 | |
| 51 | /******************************************************************************* |
| 52 | * Grand array that holds the platform's topology information for state |
| 53 | * management of affinity instances. Each node (aff_map_node) in the array |
| 54 | * corresponds to an affinity instance e.g. cluster, cpu within an mpidr |
| 55 | ******************************************************************************/ |
| 56 | aff_map_node psci_aff_map[PSCI_NUM_AFFS] |
| 57 | __attribute__ ((section("tzfw_coherent_mem"))); |
| 58 | |
| 59 | /******************************************************************************* |
| 60 | * In a system, a certain number of affinity instances are present at an |
| 61 | * affinity level. The cumulative number of instances across all levels are |
| 62 | * stored in 'psci_aff_map'. The topology tree has been flattenned into this |
| 63 | * array. To retrieve nodes, information about the extents of each affinity |
| 64 | * level i.e. start index and end index needs to be present. 'psci_aff_limits' |
| 65 | * stores this information. |
| 66 | ******************************************************************************/ |
| 67 | aff_limits_node psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Pointer to functions exported by the platform to complete power mgmt. ops |
| 71 | ******************************************************************************/ |
| 72 | plat_pm_ops *psci_plat_pm_ops; |
| 73 | |
| 74 | /******************************************************************************* |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 75 | * Routine to return the maximum affinity level to traverse to after a cpu has |
| 76 | * been physically powered up. It is expected to be called immediately after |
| 77 | * reset from assembler code. It has to find its 'aff_map_node' instead of |
| 78 | * getting it as an argument. |
| 79 | * TODO: Calling psci_get_aff_map_node() with the MMU disabled is slow. Add |
| 80 | * support to allow faster access to the target affinity level. |
| 81 | ******************************************************************************/ |
| 82 | int get_power_on_target_afflvl(unsigned long mpidr) |
| 83 | { |
| 84 | aff_map_node *node; |
| 85 | unsigned int state; |
| 86 | |
| 87 | /* Retrieve our node from the topology tree */ |
| 88 | node = psci_get_aff_map_node(mpidr & MPIDR_AFFINITY_MASK, MPIDR_AFFLVL0); |
| 89 | assert(node); |
| 90 | |
| 91 | /* |
| 92 | * Return the maximum supported affinity level if this cpu was off. |
| 93 | * Call the handler in the suspend code if this cpu had been suspended. |
| 94 | * Any other state is invalid. |
| 95 | */ |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 96 | state = psci_get_state(node); |
Achin Gupta | a45e397 | 2013-12-05 15:10:48 +0000 | [diff] [blame] | 97 | if (state == PSCI_STATE_ON_PENDING) |
| 98 | return get_max_afflvl(); |
| 99 | |
| 100 | if (state == PSCI_STATE_SUSPEND) |
| 101 | return psci_get_suspend_afflvl(node); |
| 102 | |
| 103 | return PSCI_E_INVALID_PARAMS; |
| 104 | } |
| 105 | |
| 106 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 107 | * Simple routine to retrieve the maximum affinity level supported by the |
| 108 | * platform and check that it makes sense. |
| 109 | ******************************************************************************/ |
| 110 | int get_max_afflvl() |
| 111 | { |
| 112 | int aff_lvl; |
| 113 | |
| 114 | aff_lvl = plat_get_max_afflvl(); |
| 115 | assert(aff_lvl <= MPIDR_MAX_AFFLVL && aff_lvl >= MPIDR_AFFLVL0); |
| 116 | |
| 117 | return aff_lvl; |
| 118 | } |
| 119 | |
| 120 | /******************************************************************************* |
| 121 | * Simple routine to set the id of an affinity instance at a given level in the |
| 122 | * mpidr. |
| 123 | ******************************************************************************/ |
| 124 | unsigned long mpidr_set_aff_inst(unsigned long mpidr, |
| 125 | unsigned char aff_inst, |
| 126 | int aff_lvl) |
| 127 | { |
| 128 | unsigned long aff_shift; |
| 129 | |
| 130 | assert(aff_lvl <= MPIDR_AFFLVL3); |
| 131 | |
| 132 | /* |
| 133 | * Decide the number of bits to shift by depending upon |
| 134 | * the affinity level |
| 135 | */ |
| 136 | aff_shift = get_afflvl_shift(aff_lvl); |
| 137 | |
| 138 | /* Clear the existing affinity instance & set the new one*/ |
| 139 | mpidr &= ~(MPIDR_AFFLVL_MASK << aff_shift); |
| 140 | mpidr |= aff_inst << aff_shift; |
| 141 | |
| 142 | return mpidr; |
| 143 | } |
| 144 | |
| 145 | /******************************************************************************* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 146 | * This function sanity checks a range of affinity levels. |
| 147 | ******************************************************************************/ |
| 148 | int psci_check_afflvl_range(int start_afflvl, int end_afflvl) |
| 149 | { |
| 150 | /* Sanity check the parameters passed */ |
| 151 | if (end_afflvl > MPIDR_MAX_AFFLVL) |
| 152 | return PSCI_E_INVALID_PARAMS; |
| 153 | |
| 154 | if (start_afflvl < MPIDR_AFFLVL0) |
| 155 | return PSCI_E_INVALID_PARAMS; |
| 156 | |
| 157 | if (end_afflvl < start_afflvl) |
| 158 | return PSCI_E_INVALID_PARAMS; |
| 159 | |
| 160 | return PSCI_E_SUCCESS; |
| 161 | } |
| 162 | |
| 163 | /******************************************************************************* |
| 164 | * This function is passed an array of pointers to affinity level nodes in the |
| 165 | * topology tree for an mpidr. It picks up locks for each affinity level bottom |
| 166 | * up in the range specified. |
| 167 | ******************************************************************************/ |
| 168 | void psci_acquire_afflvl_locks(unsigned long mpidr, |
| 169 | int start_afflvl, |
| 170 | int end_afflvl, |
| 171 | mpidr_aff_map_nodes mpidr_nodes) |
| 172 | { |
| 173 | int level; |
| 174 | |
| 175 | for (level = start_afflvl; level <= end_afflvl; level++) { |
| 176 | if (mpidr_nodes[level] == NULL) |
| 177 | continue; |
| 178 | bakery_lock_get(mpidr, &mpidr_nodes[level]->lock); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | /******************************************************************************* |
| 183 | * This function is passed an array of pointers to affinity level nodes in the |
| 184 | * topology tree for an mpidr. It releases the lock for each affinity level top |
| 185 | * down in the range specified. |
| 186 | ******************************************************************************/ |
| 187 | void psci_release_afflvl_locks(unsigned long mpidr, |
| 188 | int start_afflvl, |
| 189 | int end_afflvl, |
| 190 | mpidr_aff_map_nodes mpidr_nodes) |
| 191 | { |
| 192 | int level; |
| 193 | |
| 194 | for (level = end_afflvl; level >= start_afflvl; level--) { |
| 195 | if (mpidr_nodes[level] == NULL) |
| 196 | continue; |
| 197 | bakery_lock_release(mpidr, &mpidr_nodes[level]->lock); |
| 198 | } |
| 199 | } |
| 200 | |
| 201 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 202 | * Simple routine to determine whether an affinity instance at a given level |
| 203 | * in an mpidr exists or not. |
| 204 | ******************************************************************************/ |
| 205 | int psci_validate_mpidr(unsigned long mpidr, int level) |
| 206 | { |
| 207 | aff_map_node *node; |
| 208 | |
| 209 | node = psci_get_aff_map_node(mpidr, level); |
| 210 | if (node && (node->state & PSCI_AFF_PRESENT)) |
| 211 | return PSCI_E_SUCCESS; |
| 212 | else |
| 213 | return PSCI_E_INVALID_PARAMS; |
| 214 | } |
| 215 | |
| 216 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | * This function retrieves all the stashed information needed to correctly |
| 218 | * resume a cpu's execution in the non-secure state after it has been physically |
| 219 | * powered on i.e. turned ON or resumed from SUSPEND |
| 220 | ******************************************************************************/ |
Achin Gupta | c8afc78 | 2013-11-25 18:45:02 +0000 | [diff] [blame] | 221 | void psci_get_ns_entry_info(unsigned int index) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | { |
| 223 | unsigned long sctlr = 0, scr, el_status, id_aa64pfr0; |
Achin Gupta | c8afc78 | 2013-11-25 18:45:02 +0000 | [diff] [blame] | 224 | gp_regs *ns_gp_regs; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 225 | |
| 226 | scr = read_scr(); |
| 227 | |
| 228 | /* Switch to the non-secure view of the registers */ |
| 229 | write_scr(scr | SCR_NS_BIT); |
| 230 | |
| 231 | /* Find out which EL we are going to */ |
| 232 | id_aa64pfr0 = read_id_aa64pfr0_el1(); |
| 233 | el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & |
| 234 | ID_AA64PFR0_ELX_MASK; |
| 235 | |
| 236 | /* Restore endianess */ |
| 237 | if (psci_ns_entry_info[index].sctlr & SCTLR_EE_BIT) |
| 238 | sctlr |= SCTLR_EE_BIT; |
| 239 | else |
| 240 | sctlr &= ~SCTLR_EE_BIT; |
| 241 | |
| 242 | /* Turn off MMU and Caching */ |
| 243 | sctlr &= ~(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_M_BIT); |
| 244 | |
| 245 | /* Set the register width */ |
| 246 | if (psci_ns_entry_info[index].scr & SCR_RW_BIT) |
| 247 | scr |= SCR_RW_BIT; |
| 248 | else |
| 249 | scr &= ~SCR_RW_BIT; |
| 250 | |
| 251 | scr |= SCR_NS_BIT; |
| 252 | |
| 253 | if (el_status) |
| 254 | write_sctlr_el2(sctlr); |
| 255 | else |
| 256 | write_sctlr_el1(sctlr); |
| 257 | |
| 258 | /* Fulfill the cpu_on entry reqs. as per the psci spec */ |
| 259 | write_scr(scr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 260 | write_elr(psci_ns_entry_info[index].eret_info.entrypoint); |
| 261 | |
Achin Gupta | c8afc78 | 2013-11-25 18:45:02 +0000 | [diff] [blame] | 262 | /* |
| 263 | * Set the general purpose registers to ~0 upon entry into the |
| 264 | * non-secure world except for x0 which should contain the |
| 265 | * context id & spsr. This is done directly on the "would be" |
| 266 | * stack pointer. Prior to entry into the non-secure world, an |
| 267 | * offset equivalent to the size of the 'gp_regs' structure is |
| 268 | * added to the sp. This general purpose register context is |
| 269 | * retrieved then. |
| 270 | */ |
| 271 | ns_gp_regs = (gp_regs *) platform_get_stack(read_mpidr()); |
| 272 | ns_gp_regs--; |
| 273 | memset(ns_gp_regs, ~0, sizeof(*ns_gp_regs)); |
| 274 | ns_gp_regs->x0 = psci_ns_entry_info[index].context_id; |
| 275 | ns_gp_regs->spsr = psci_ns_entry_info[index].eret_info.spsr; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 276 | } |
| 277 | |
| 278 | /******************************************************************************* |
| 279 | * This function retrieves and stashes all the information needed to correctly |
| 280 | * resume a cpu's execution in the non-secure state after it has been physically |
| 281 | * powered on i.e. turned ON or resumed from SUSPEND. This is done prior to |
| 282 | * turning it on or before suspending it. |
| 283 | ******************************************************************************/ |
| 284 | int psci_set_ns_entry_info(unsigned int index, |
| 285 | unsigned long entrypoint, |
| 286 | unsigned long context_id) |
| 287 | { |
| 288 | int rc = PSCI_E_SUCCESS; |
| 289 | unsigned int rw, mode, ee, spsr = 0; |
| 290 | unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1(), scr = read_scr(); |
| 291 | unsigned long el_status; |
| 292 | |
| 293 | /* Figure out what mode do we enter the non-secure world in */ |
| 294 | el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & |
| 295 | ID_AA64PFR0_ELX_MASK; |
| 296 | |
| 297 | /* |
| 298 | * Figure out whether the cpu enters the non-secure address space |
| 299 | * in aarch32 or aarch64 |
| 300 | */ |
| 301 | rw = scr & SCR_RW_BIT; |
| 302 | if (rw) { |
| 303 | |
| 304 | /* |
| 305 | * Check whether a Thumb entry point has been provided for an |
| 306 | * aarch64 EL |
| 307 | */ |
| 308 | if (entrypoint & 0x1) |
| 309 | return PSCI_E_INVALID_PARAMS; |
| 310 | |
| 311 | if (el_status && (scr & SCR_HCE_BIT)) { |
| 312 | mode = MODE_EL2; |
| 313 | ee = read_sctlr_el2() & SCTLR_EE_BIT; |
| 314 | } else { |
| 315 | mode = MODE_EL1; |
| 316 | ee = read_sctlr_el1() & SCTLR_EE_BIT; |
| 317 | } |
| 318 | |
| 319 | spsr = DAIF_DBG_BIT | DAIF_ABT_BIT; |
| 320 | spsr |= DAIF_IRQ_BIT | DAIF_FIQ_BIT; |
| 321 | spsr <<= PSR_DAIF_SHIFT; |
| 322 | spsr |= make_spsr(mode, MODE_SP_ELX, !rw); |
| 323 | |
| 324 | psci_ns_entry_info[index].sctlr |= ee; |
| 325 | psci_ns_entry_info[index].scr |= SCR_RW_BIT; |
| 326 | } else { |
| 327 | |
| 328 | /* Check whether aarch32 has to be entered in Thumb mode */ |
| 329 | if (entrypoint & 0x1) |
| 330 | spsr = SPSR32_T_BIT; |
| 331 | |
| 332 | if (el_status && (scr & SCR_HCE_BIT)) { |
| 333 | mode = AARCH32_MODE_HYP; |
| 334 | ee = read_sctlr_el2() & SCTLR_EE_BIT; |
| 335 | } else { |
| 336 | mode = AARCH32_MODE_SVC; |
| 337 | ee = read_sctlr_el1() & SCTLR_EE_BIT; |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * TODO: Choose async. exception bits if HYP mode is not |
| 342 | * implemented according to the values of SCR.{AW, FW} bits |
| 343 | */ |
| 344 | spsr |= DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; |
| 345 | spsr <<= PSR_DAIF_SHIFT; |
| 346 | if(ee) |
| 347 | spsr |= SPSR32_EE_BIT; |
| 348 | spsr |= mode; |
| 349 | |
| 350 | /* Ensure that the CSPR.E and SCTLR.EE bits match */ |
| 351 | psci_ns_entry_info[index].sctlr |= ee; |
| 352 | psci_ns_entry_info[index].scr &= ~SCR_RW_BIT; |
| 353 | } |
| 354 | |
| 355 | psci_ns_entry_info[index].eret_info.entrypoint = entrypoint; |
| 356 | psci_ns_entry_info[index].eret_info.spsr = spsr; |
| 357 | psci_ns_entry_info[index].context_id = context_id; |
| 358 | |
| 359 | return rc; |
| 360 | } |
| 361 | |
| 362 | /******************************************************************************* |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 363 | * This function takes a pointer to an affinity node in the topology tree and |
| 364 | * returns its state. State of a non-leaf node needs to be calculated. |
| 365 | ******************************************************************************/ |
| 366 | unsigned short psci_get_state(aff_map_node *node) |
| 367 | { |
| 368 | assert(node->level >= MPIDR_AFFLVL0 && node->level <= MPIDR_MAX_AFFLVL); |
| 369 | |
| 370 | /* A cpu node just contains the state which can be directly returned */ |
| 371 | if (node->level == MPIDR_AFFLVL0) |
| 372 | return (node->state >> PSCI_STATE_SHIFT) & PSCI_STATE_MASK; |
| 373 | |
| 374 | /* |
| 375 | * For an affinity level higher than a cpu, the state has to be |
| 376 | * calculated. It depends upon the value of the reference count |
| 377 | * which is managed by each node at the next lower affinity level |
| 378 | * e.g. for a cluster, each cpu increments/decrements the reference |
| 379 | * count. If the reference count is 0 then the affinity level is |
| 380 | * OFF else ON. |
| 381 | */ |
| 382 | if (node->ref_count) |
| 383 | return PSCI_STATE_ON; |
| 384 | else |
| 385 | return PSCI_STATE_OFF; |
| 386 | } |
| 387 | |
| 388 | /******************************************************************************* |
| 389 | * This function takes a pointer to an affinity node in the topology tree and |
| 390 | * a target state. State of a non-leaf node needs to be converted to a reference |
| 391 | * count. State of a leaf node can be set directly. |
| 392 | ******************************************************************************/ |
| 393 | void psci_set_state(aff_map_node *node, unsigned short state) |
| 394 | { |
| 395 | assert(node->level >= MPIDR_AFFLVL0 && node->level <= MPIDR_MAX_AFFLVL); |
| 396 | |
| 397 | /* |
| 398 | * For an affinity level higher than a cpu, the state is used |
| 399 | * to decide whether the reference count is incremented or |
| 400 | * decremented. Entry into the ON_PENDING state does not have |
| 401 | * effect. |
| 402 | */ |
| 403 | if (node->level > MPIDR_AFFLVL0) { |
| 404 | switch (state) { |
| 405 | case PSCI_STATE_ON: |
| 406 | node->ref_count++; |
| 407 | break; |
| 408 | case PSCI_STATE_OFF: |
| 409 | case PSCI_STATE_SUSPEND: |
| 410 | node->ref_count--; |
| 411 | break; |
| 412 | case PSCI_STATE_ON_PENDING: |
| 413 | /* |
| 414 | * An affinity level higher than a cpu will not undergo |
| 415 | * a state change when it is about to be turned on |
| 416 | */ |
| 417 | return; |
| 418 | default: |
| 419 | assert(0); |
| 420 | } |
| 421 | } else { |
| 422 | node->state &= ~(PSCI_STATE_MASK << PSCI_STATE_SHIFT); |
| 423 | node->state |= (state & PSCI_STATE_MASK) << PSCI_STATE_SHIFT; |
| 424 | } |
| 425 | } |
| 426 | |
| 427 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 428 | * An affinity level could be on, on_pending, suspended or off. These are the |
Achin Gupta | 3140a9e | 2013-12-02 16:23:12 +0000 | [diff] [blame] | 429 | * logical states it can be in. Physically either it is off or on. When it is in |
| 430 | * the state on_pending then it is about to be turned on. It is not possible to |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 431 | * tell whether that's actually happenned or not. So we err on the side of |
| 432 | * caution & treat the affinity level as being turned off. |
| 433 | ******************************************************************************/ |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 434 | unsigned short psci_get_phys_state(aff_map_node *node) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 435 | { |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 436 | unsigned int state; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 437 | |
Achin Gupta | 75f7367 | 2013-12-05 16:33:10 +0000 | [diff] [blame] | 438 | state = psci_get_state(node); |
| 439 | return get_phys_state(state); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | /******************************************************************************* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 443 | * This function takes an array of pointers to affinity instance nodes in the |
| 444 | * topology tree and calls the physical power on handler for the corresponding |
| 445 | * affinity levels |
| 446 | ******************************************************************************/ |
| 447 | static int psci_call_power_on_handlers(mpidr_aff_map_nodes mpidr_nodes, |
| 448 | int start_afflvl, |
| 449 | int end_afflvl, |
| 450 | afflvl_power_on_finisher *pon_handlers, |
| 451 | unsigned long mpidr) |
| 452 | { |
| 453 | int rc = PSCI_E_INVALID_PARAMS, level; |
| 454 | aff_map_node *node; |
| 455 | |
| 456 | for (level = end_afflvl; level >= start_afflvl; level--) { |
| 457 | node = mpidr_nodes[level]; |
| 458 | if (node == NULL) |
| 459 | continue; |
| 460 | |
| 461 | /* |
| 462 | * If we run into any trouble while powering up an |
| 463 | * affinity instance, then there is no recovery path |
| 464 | * so simply return an error and let the caller take |
| 465 | * care of the situation. |
| 466 | */ |
| 467 | rc = pon_handlers[level](mpidr, node); |
| 468 | if (rc != PSCI_E_SUCCESS) |
| 469 | break; |
| 470 | } |
| 471 | |
| 472 | return rc; |
| 473 | } |
| 474 | |
| 475 | /******************************************************************************* |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 476 | * Generic handler which is called when a cpu is physically powered on. It |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 477 | * traverses through all the affinity levels performing generic, architectural, |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 478 | * platform setup and state management e.g. for a cluster that's been powered |
| 479 | * on, it will call the platform specific code which will enable coherency at |
| 480 | * the interconnect level. For a cpu it could mean turning on the MMU etc. |
| 481 | * |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 482 | * The state of all the relevant affinity levels is changed after calling the |
| 483 | * affinity level specific handlers as their actions would depend upon the state |
| 484 | * the affinity level is exiting from. |
| 485 | * |
| 486 | * The affinity level specific handlers are called in descending order i.e. from |
| 487 | * the highest to the lowest affinity level implemented by the platform because |
| 488 | * to turn on affinity level X it is neccesary to turn on affinity level X + 1 |
| 489 | * first. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 490 | * |
| 491 | * CAUTION: This function is called with coherent stacks so that coherency and |
| 492 | * the mmu can be turned on safely. |
| 493 | ******************************************************************************/ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 494 | void psci_afflvl_power_on_finish(unsigned long mpidr, |
| 495 | int start_afflvl, |
| 496 | int end_afflvl, |
| 497 | afflvl_power_on_finisher *pon_handlers) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 498 | { |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 499 | mpidr_aff_map_nodes mpidr_nodes; |
| 500 | int rc; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 501 | |
| 502 | mpidr &= MPIDR_AFFINITY_MASK;; |
| 503 | |
| 504 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 505 | * Collect the pointers to the nodes in the topology tree for |
| 506 | * each affinity instance in the mpidr. If this function does |
| 507 | * not return successfully then either the mpidr or the affinity |
| 508 | * levels are incorrect. Either case is an irrecoverable error. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 509 | */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 510 | rc = psci_get_aff_map_nodes(mpidr, |
| 511 | start_afflvl, |
| 512 | end_afflvl, |
| 513 | mpidr_nodes); |
| 514 | assert (rc == PSCI_E_SUCCESS); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 515 | |
| 516 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 517 | * This function acquires the lock corresponding to each affinity |
| 518 | * level so that by the time all locks are taken, the system topology |
| 519 | * is snapshot and state management can be done safely. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 520 | */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 521 | psci_acquire_afflvl_locks(mpidr, |
| 522 | start_afflvl, |
| 523 | end_afflvl, |
| 524 | mpidr_nodes); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 525 | |
| 526 | /* Perform generic, architecture and platform specific handling */ |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 527 | rc = psci_call_power_on_handlers(mpidr_nodes, |
| 528 | start_afflvl, |
| 529 | end_afflvl, |
| 530 | pon_handlers, |
| 531 | mpidr); |
| 532 | assert (rc == PSCI_E_SUCCESS); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 533 | |
| 534 | /* |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 535 | * This loop releases the lock corresponding to each affinity level |
| 536 | * in the reverse order to which they were acquired. |
| 537 | */ |
| 538 | psci_release_afflvl_locks(mpidr, |
| 539 | start_afflvl, |
| 540 | end_afflvl, |
| 541 | mpidr_nodes); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 542 | } |