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git01.mediatek.com / filogic / atf / df2db56d55c321ee5ef77eb847a1afb5f7e18e61 / . / plat / arm / css / sgi / sgi_bl31_setup.c
blob: 8fa5b01b277d9e113946ef7b02d88cda10b61748 [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1/*
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]9#include <libfdt.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10
11#include <common/bl_common.h>
12#include <common/debug.h>
Antonio Nino Diaz1b0c6f12019-01-23 21:08:43 +0000[diff] [blame]13#include <drivers/arm/css/css_mhu_doorbell.h>
Antonio Nino Diazc30db5b2019-01-23 20:37:32 +0000[diff] [blame]14#include <drivers/arm/css/scmi.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]15#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]16
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]17#include <sgi_ras.h>
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]18#include <sgi_variant.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]19
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]20sgi_platform_info_t sgi_plat_info;
21
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]22static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
23 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
24 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
25 .db_preserve_mask = 0xfffffffe,
26 .db_modify_mask = 0x1,
27 .ring_doorbell = &mhu_ring_doorbell,
28};
29
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]30static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info = {
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]31 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
32 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
33 .db_preserve_mask = 0xfffffffe,
34 .db_modify_mask = 0x1,
35 .ring_doorbell = &mhuv2_ring_doorbell,
36};
37
Chandni Cherukuri61f3a7c2018-10-11 14:08:08 +0530[diff] [blame]38scmi_channel_plat_info_t *plat_css_get_scmi_info()
39{
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]40 if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM)
41 return &rd_n1e1_edge_scmi_plat_info;
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]42 else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
43 return &sgi575_scmi_plat_info;
44 else
45 panic();
46};
47
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]48void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
49 u_register_t arg2, u_register_t arg3)
50{
Chandni Cherukuri3aa09f72018-11-28 11:31:51 +0530[diff] [blame]51 sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
52 sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
Chandni Cherukuric8ef0452018-10-04 16:32:03 +0530[diff] [blame]53
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]54 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
55}
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]56
57void bl31_platform_setup(void)
58{
59 arm_bl31_platform_setup();
60
61#if RAS_EXTENSION
62 sgi_ras_intr_handler_setup();
63#endif
64}
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]65
66const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
67{
Chandni Cherukuri346a7cc2019-02-27 13:59:11 +0530[diff] [blame]68 /* For RD-E1-Edge platform only CPU ON/OFF is supported */
69 if ((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
70 (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) {
Chandni Cherukuri2dfe1d02018-11-22 10:15:25 +0530[diff] [blame]71 ops->cpu_standby = NULL;
72 ops->system_off = NULL;
73 ops->system_reset = NULL;
74 ops->get_sys_suspend_power_state = NULL;
75 ops->pwr_domain_suspend = NULL;
76 ops->pwr_domain_suspend_finish = NULL;
77 }
78
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +0530[diff] [blame]79 return css_scmi_override_pm_ops(ops);
80}