blob: 8dac9439dd19a61b17e32f74e68d5d2cd3b9885d [file] [log] [blame]
Anson Huang73b18532018-06-05 16:13:45 +08001/*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl_common.h>
10#include <cci.h>
11#include <console.h>
12#include <context.h>
13#include <context_mgmt.h>
14#include <debug.h>
15#include <imx8qx_pads.h>
16#include <imx8_iomux.h>
17#include <imx8_lpuart.h>
18#include <mmio.h>
19#include <platform.h>
20#include <platform_def.h>
21#include <plat_imx8.h>
22#include <sci/sci.h>
23#include <sec_rsrc.h>
24#include <stdbool.h>
25#include <xlat_tables.h>
26
27IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
28IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
29IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
30IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
31IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
32IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
33
34static entry_point_info_t bl32_image_ep_info;
35static entry_point_info_t bl33_image_ep_info;
36
37#define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
38 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
39 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
40 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
41 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
42
43static const mmap_region_t imx_mmap[] = {
44 MAP_REGION_FLAT(IMX_BOOT_UART_BASE, IMX_BOOT_UART_SIZE, MT_DEVICE | MT_RW),
45 MAP_REGION_FLAT(SC_IPC_BASE, SC_IPC_SIZE, MT_DEVICE | MT_RW),
46 MAP_REGION_FLAT(PLAT_GICD_BASE, PLAT_GICD_SIZE, MT_DEVICE | MT_RW),
47 MAP_REGION_FLAT(PLAT_GICR_BASE, PLAT_GICR_SIZE, MT_DEVICE | MT_RW),
48 {0}
49};
50
51static uint32_t get_spsr_for_bl33_entry(void)
52{
53 unsigned long el_status;
54 unsigned long mode;
55 uint32_t spsr;
56
57 /* figure out what mode we enter the non-secure world */
58 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
59 el_status &= ID_AA64PFR0_ELX_MASK;
60
61 mode = (el_status) ? MODE_EL2 : MODE_EL1;
62
63 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
64 return spsr;
65}
66
67#if DEBUG_CONSOLE_A35
68static void lpuart32_serial_setbrg(unsigned int base, int baudrate)
69{
70 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr;
71 unsigned int diff1, diff2, tmp, rate;
72
73 if (baudrate == 0)
74 panic();
75
76 sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
77
78 baud_diff = baudrate;
79 osr = 0;
80 sbr = 0;
81 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
82 tmp_sbr = (rate / (baudrate * tmp_osr));
83 if (tmp_sbr == 0)
84 tmp_sbr = 1;
85
86 /* calculate difference in actual baud w/ current values */
87 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate;
88 diff2 = rate / (tmp_osr * (tmp_sbr + 1));
89
90 /* select best values between sbr and sbr+1 */
91 if (diff1 > (baudrate - diff2)) {
92 diff1 = baudrate - diff2;
93 tmp_sbr++;
94 }
95
96 if (diff1 <= baud_diff) {
97 baud_diff = diff1;
98 osr = tmp_osr;
99 sbr = tmp_sbr;
100 }
101 }
102
103 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD);
104
105 if ((osr > 3) && (osr < 8))
106 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
107
108 tmp &= ~LPUART_BAUD_OSR_MASK;
109 tmp |= LPUART_BAUD_OSR(osr - 1);
110 tmp &= ~LPUART_BAUD_SBR_MASK;
111 tmp |= LPUART_BAUD_SBR(sbr);
112
113 /* explicitly disable 10 bit mode & set 1 stop bit */
114 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
115
116 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp);
117}
118
119static int lpuart32_serial_init(unsigned int base)
120{
121 unsigned int tmp;
122
123 /* disable TX & RX before enabling clocks */
124 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
125 tmp &= ~(CTRL_TE | CTRL_RE);
126 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
127
128 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0);
129 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE));
130
131 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0);
132
133 /* provide data bits, parity, stop bit, etc */
134 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE);
135
136 /* eight data bits no parity bit */
137 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
138 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
139 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
140
141 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE);
142
143 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
144 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
145 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A);
146
147 return 0;
148}
149#endif
150
151void imx8_partition_resources(void)
152{
153 sc_rm_pt_t secure_part, os_part;
154 sc_rm_mr_t mr, mr_record = 64;
155 sc_faddr_t start, end;
156 sc_err_t err;
157 bool owned;
158 int i;
159
160 err = sc_rm_get_partition(ipc_handle, &secure_part);
161 if (err)
162 ERROR("sc_rm_get_partition failed: %u\n", err);
163
164 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,
165 false, false, false);
166 if (err)
167 ERROR("sc_rm_partition_alloc failed: %u\n", err);
168
169 err = sc_rm_set_parent(ipc_handle, os_part, secure_part);
170 if (err)
171 ERROR("sc_rm_set_parent: %u\n", err);
172
173 /* set secure resources to NOT-movable */
174 for (i = 0; i < (ARRAY_SIZE(secure_rsrcs)); i++) {
175 err = sc_rm_set_resource_movable(ipc_handle,
176 secure_rsrcs[i], secure_rsrcs[i], false);
177 if (err)
178 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
179 secure_rsrcs[i], err);
180 }
181
182 /* move all movable resources and pins to non-secure partition */
183 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);
184 if (err)
185 ERROR("sc_rm_move_all: %u\n", err);
186
187 /* iterate through peripherals to give NS OS part access */
188 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) {
189 err = sc_rm_set_peripheral_permissions(ipc_handle,
190 ns_access_allowed[i], os_part, SC_RM_PERM_FULL);
191 if (err)
192 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \
193 ret %u\n", ns_access_allowed[i], err);
194 }
195
196 /*
197 * sc_rm_set_peripheral_permissions
198 * sc_rm_set_memreg_permissions
199 * sc_rm_set_pin_movable
200 */
201 for (mr = 0; mr < 64; mr++) {
202 owned = sc_rm_is_memreg_owned(ipc_handle, mr);
203 if (owned) {
204 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
205 if (err)
206 ERROR("Memreg get info failed, %u\n", mr);
207
208 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
209 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
210 mr_record = mr; /* Record the mr for ATF running */
211 } else {
212 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
213 if (err)
214 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
215 err %d\n", start, end, err);
216 }
217 }
218 }
219
220 if (mr_record != 64) {
221 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);
222 if (err)
223 ERROR("Memreg get info failed, %u\n", mr_record);
224 if ((BL31_LIMIT - 1) < end) {
225 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
226 if (err)
227 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
228 (sc_faddr_t)BL31_LIMIT, end);
229 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
230 if (err)
231 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
232 (sc_faddr_t)BL31_LIMIT, end);
233 }
234
235 if (start < (BL31_BASE - 1)) {
236 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
237 if (err)
238 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
239 start, (sc_faddr_t)BL31_BASE - 1);
240 err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
241 if (err)
242 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
243 start, (sc_faddr_t)BL31_BASE - 1);
244 }
245 }
246
247 if (err)
248 NOTICE("Partitioning Failed\n");
249 else
250 NOTICE("Non-secure Partitioning Succeeded\n");
251}
252
253void bl31_early_platform_setup(bl31_params_t *from_bl2,
254 void *plat_params_from_bl2)
255{
256#if DEBUG_CONSOLE
257 static console_lpuart_t console;
258#endif
259 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
260 panic();
261
262#if DEBUG_CONSOLE_A35
263 sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON);
264 sc_pm_clock_rate_t rate = 80000000;
265 sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
266 sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false);
267
268 /* Configure UART pads */
269 sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL);
270 sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL);
271 lpuart32_serial_init(IMX_BOOT_UART_BASE);
272#endif
273
274#if DEBUG_CONSOLE
275 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
276 IMX_CONSOLE_BAUDRATE, &console);
277#endif
278 /* Turn on MU1 for non-secure OS/Hypervisor */
279 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
280
281 /*
282 * create new partition for non-secure OS/Hypervisor
283 * uses global structs defined in sec_rsrc.h
284 */
285 imx8_partition_resources();
286
287 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
288 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
289 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
290}
291
292void bl31_plat_arch_setup(void)
293{
294 unsigned long ro_start = BL31_RO_START;
295 unsigned long ro_size = BL31_RO_END - BL31_RO_START;
296 unsigned long rw_start = BL31_RW_START;
297 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
298#if USE_COHERENT_MEM
299 unsigned long coh_start = BL31_COHERENT_RAM_START;
300 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START;
301#endif
302
303 mmap_add_region(ro_start, ro_start, ro_size,
304 MT_RO | MT_MEMORY | MT_SECURE);
305 mmap_add_region(rw_start, rw_start, rw_size,
306 MT_RW | MT_MEMORY | MT_SECURE);
307 mmap_add(imx_mmap);
308
309#if USE_COHERENT_MEM
310 mmap_add_region(coh_start, coh_start, coh_size,
311 MT_DEVICE | MT_RW | MT_SECURE);
312#endif
313
314 init_xlat_tables();
315 enable_mmu_el3(0);
316}
317
318void bl31_platform_setup(void)
319{
320 plat_gic_driver_init();
321 plat_gic_init();
322}
323
324entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
325{
326 if (type == NON_SECURE)
327 return &bl33_image_ep_info;
328 if (type == SECURE)
329 return &bl32_image_ep_info;
330
331 return NULL;
332}
333
334unsigned int plat_get_syscnt_freq2(void)
335{
336 return COUNTER_FREQUENCY;
337}
338
339void bl31_plat_runtime_setup(void)
340{
341 return;
342}