blob: faddb88c2d23e661c71f3c1189ae498e9d0ac12b [file] [log] [blame]
rutigl@gmail.comdefbeed2023-03-19 09:19:05 +02001/*
2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * Copyright (C) 2017-2023 Nuvoton Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef NPCM845x_ARM_DEF_H
10#define NPCM845x_ARM_DEF_H
11
12#include <arch.h>
13#include <common/interrupt_props.h>
14#include <common/tbbr/tbbr_img_def.h>
15#include <drivers/arm/gic_common.h>
16#include <lib/utils_def.h>
17#include <lib/xlat_tables/xlat_tables_defs.h>
18#include <plat/arm/common/smccc_def.h>
19#include <plat/common/common_def.h>
20
21/* This flag will add zones to the MMU so that it will be possible to debug */
22#ifdef NPCM845X_DEBUG
23#define ALLOW_DEBUG_MMU
24#undef ALLOW_DEBUG_MMU
25#endif /* NPCM845X_DEBUG */
26
27#undef CONFIG_TARGET_ARBEL_PALLADIUM
28/******************************************************************************
29 * Definitions common to all ARM standard platforms
30 *****************************************************************************/
31
32/*
33 * Root of trust key hash lengths
34 */
35#define ARM_ROTPK_HEADER_LEN 19
36#define ARM_ROTPK_HASH_LEN 32
37
38/* Special value used to verify platform parameters from BL2 to BL31 */
39#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
40
41/* No need for system because we have only one cluster */
42#define ARM_SYSTEM_COUNT U(0)
43
44#define ARM_CACHE_WRITEBACK_SHIFT 6
45
46/*
47 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels.
48 * The power levels have a 1:1 mapping with the MPIDR affinity levels.
49 */
50/* In NPCM845x - refers to cores */
51#define ARM_PWR_LVL0 MPIDR_AFFLVL0
52
53/* In NPCM845x - refers to cluster */
54#define ARM_PWR_LVL1 MPIDR_AFFLVL1
55
56/* No need for additional settings because the platform doesn't have system */
57
58/*
59 * Macros for local power states in ARM platforms encoded by State-ID field
60 * within the power-state parameter.
61 */
62#define NPCM845x_PLAT_PRIMARY_CPU U(0x0)
63#define NPCM845x_CLUSTER_COUNT U(1)
64
65#ifdef SECONDARY_BRINGUP
66#define NPCM845x_MAX_CPU_PER_CLUSTER U(2)
67#define NPCM845x_PLATFORM_CORE_COUNT U(2)
68#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2)
69#else
70#define NPCM845x_MAX_CPU_PER_CLUSTER U(4)
71#define NPCM845x_PLATFORM_CORE_COUNT U(4)
72#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4)
73#endif /* SECONDARY_BRINGUP */
74
75#define NPCM845x_SYSTEM_COUNT U(0)
76
77/* Memory mapping for NPCM845x */
78#define NPCM845x_REG_BASE 0xf0000000
79#define NPCM845x_REG_SIZE 0x0ff16000
80
81/*
82 * DRAM
83 * 0x3fffffff +-------------+
84 * | BL33 | (non-secure)
85 * 0x06200000 +-------------+
86 * | BL32 SHARED | (non-secure)
87 * 0x06000000 +-------------+
88 * | BL32 | (secure)
89 * 0x02100000 +-------------+
90 * | BL31 | (secure)
91 * 0x02000000 +-------------+
92 * | | (non-secure)
93 * 0x00000000 +-------------+
94 *
95 * Trusted ROM
96 * 0xfff50000 +-------------+
97 * | BL1 (ro) |
98 * 0xfff40000 +-------------+
99 */
100
101#define ARM_DRAM1_BASE ULL(0x00000000)
102#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
103/*
104 * Although npcm845x is 4G,
105 * consider only 2G Trusted Firmware memory allocation
106 */
107#define ARM_DRAM1_SIZE ULL(0x37000000)
108#else
109#define ARM_DRAM1_SIZE ULL(0x10000000)
110#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U)
111#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
112
113/*
114 * The top 16MB of DRAM1 is configured as secure access only using the TZC
115 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
116 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
117 */
118
119/* Check for redundancy */
120#ifdef NPCM845X_DEBUG
121#define PLAT_ARM_NS_IMAGE_BASE 0x0
122#endif /* NPCM845X_DEBUG */
123
124#define ARM_TZC_DRAM1_SIZE UL(0x01000000)
125#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
126#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
127 ARM_SCP_TZC_DRAM1_SIZE - 1U)
128
129/*
130 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
131 * firmware. This region is meant to be NOLOAD and will not be zero
132 * initialized. Data sections with the attribute `arm_el3_tzc_dram`
133 * will be placed here.
134 *
135 * NPCM845x - Currently the platform doesn't have EL3 implementation
136 * on secured DRAM.
137 */
138#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
139 ARM_EL3_TZC_DRAM1_SIZE)
140#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
141#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
142 ARM_EL3_TZC_DRAM1_SIZE - 1U)
143
144#define ARM_AP_TZC_DRAM1_BASE 0x02100000
145#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
146 (ARM_SCP_TZC_DRAM1_SIZE + \
147 ARM_EL3_TZC_DRAM1_SIZE))
148#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
149 ARM_AP_TZC_DRAM1_SIZE - 1U)
150
151/* Define the Access permissions for Secure peripherals to NS_DRAM */
152#if ARM_CRYPTOCELL_INTEG
153/*
154 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
155 * This is required by CryptoCell to authenticate BL33 which is loaded
156 * into the Non Secure DDR.
157 */
158#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
159#else
160#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
161#endif /* ARM_CRYPTOCELL_INTEG */
162
163#ifdef SPD_opteed
164/*
165 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
166 * load/authenticate the trusted os extra image. The first 512KB of
167 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
168 * for OPTEE is paged image which only include the paging part using
169 * virtual memory but without "init" data. OPTEE will copy the "init" data
170 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
171 * extra image behind the "init" data.
172 */
173#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
174#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
175#define BL32_BASE ARM_AP_TZC_DRAM1_BASE
176#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
177 ARM_AP_TZC_DRAM1_SIZE)
178
179#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \
180 ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \
181 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
182#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
183#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
184 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
185 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
186 MT_MEMORY | MT_RW | MT_SECURE)
187
188/*
189 * Map the memory for the OP-TEE core (also known as OP-TEE pager
190 * when paging support is enabled).
191 */
192#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
193 BL32_BASE, BL32_LIMIT - BL32_BASE, \
194 MT_MEMORY | MT_RW | MT_SECURE)
195#endif /* SPD_opteed */
196
197#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
198#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
199 ARM_TZC_DRAM1_SIZE)
200#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
201 ARM_NS_DRAM1_SIZE - 1U)
202
203/* The platform doesn't use DRAM2 but it has to have a value for calculation */
204#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */
205#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */
206#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U)
207
208#define FIRST_EXT_INTERRUPT_NUM U(32)
209#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM)
210
211#define ARM_IRQ_SEC_SGI_0 8
212#define ARM_IRQ_SEC_SGI_1 9
213#define ARM_IRQ_SEC_SGI_2 10
214#define ARM_IRQ_SEC_SGI_3 11
215#define ARM_IRQ_SEC_SGI_4 12
216#define ARM_IRQ_SEC_SGI_5 13
217#define ARM_IRQ_SEC_SGI_6 14
218#define ARM_IRQ_SEC_SGI_7 15
219
220/*
221 * Define a list of Group 1 Secure and Group 0 interrupt properties
222 * as per GICv3 terminology. On a GICv2 system or mode,
223 * the lists will be merged and treated as Group 0 interrupts.
224 */
225#define ARM_G1S_IRQ_PROPS(grp) \
226 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
227 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
228 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
229 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
230 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
231 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
232 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
233 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
234 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
235 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
237 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
239 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
240
241#define ARM_G0_IRQ_PROPS(grp) \
242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
243 PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \
244 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
245 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
246
247#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
248 ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \
249 MT_DEVICE | MT_RW | MT_SECURE)
250
251#ifdef ALLOW_DEBUG_MMU
252/* In order to be able to debug,
253 * the platform needs to add BL33 and BL32 to MMU as well.
254 */
255#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
256 ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \
257 MT_MEMORY | MT_RW | MT_NS)
258
259#ifdef BL32_BASE
260#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \
261 BL32_BASE, BL32_LIMIT - BL32_BASE, \
262 MT_MEMORY | MT_RW | MT_SECURE)
263#endif /* BL32_BASE */
264
265#ifdef NPCM845X_DEBUG
266#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \
267 0xFFFB0000, 0x20000, \
268 MT_MEMORY | MT_RW | MT_NS)
269#endif /* NPCM845X_DEBUG */
270#endif /* BL32_BASE */
271
272#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
273 ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \
274 MT_MEMORY | MT_RW | MT_NS)
275
276#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
277 TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \
278 MT_MEMORY | MT_RW | MT_SECURE)
279
280#if ARM_BL31_IN_DRAM
281#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
282 BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \
283 MT_MEMORY | MT_RW | MT_SECURE)
284#endif /* ARM_BL31_IN_DRAM */
285
286/* Currently the platform doesn't have EL3 implementation on secured DRAM. */
287#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
288 ARM_EL3_TZC_DRAM1_BASE, \
289 ARM_EL3_TZC_DRAM1_SIZE, \
290 MT_MEMORY | MT_RW | MT_SECURE)
291
292#if defined(SPD_spmd)
293#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
294 PLAT_ARM_TRUSTED_DRAM_BASE, \
295 PLAT_ARM_TRUSTED_DRAM_SIZE, \
296 MT_MEMORY | MT_RW | MT_SECURE)
297#endif /* SPD_spmd */
298
299/*
300 * Mapping for the BL1 RW region. This mapping is needed by BL2
301 * in order to share the Mbed TLS heap. Since the heap is allocated
302 * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access
303 * to the BL1 RW region in order to be able to access the heap.
304 */
305#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
306 BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \
307 MT_MEMORY | MT_RW | EL3_PAS)
308
309/*
310 * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region
311 * for each section, otherwise one region containing both sections
312 * is defined.
313 */
314#if SEPARATE_CODE_AND_RODATA
315#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
316 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
317 MT_CODE | EL3_PAS), \
318 MAP_REGION_FLAT(BL_RO_DATA_BASE, \
319 BL_RO_DATA_END - BL_RO_DATA_BASE, \
320 MT_RO_DATA | EL3_PAS)
321#else
322#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
323 BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
324 MT_CODE | EL3_PAS)
325#endif /* SEPARATE_CODE_AND_RODATA */
326
327#if USE_COHERENT_MEM
328#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
329 BL_COHERENT_RAM_BASE, \
330 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
331 MT_DEVICE | MT_RW | EL3_PAS)
332#endif /* USE_COHERENT_MEM */
333
334#if USE_ROMLIB
335#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
336 ROMLIB_RO_BASE, \
337 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \
338 MT_CODE | MT_SECURE)
339
340#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
341 ROMLIB_RW_BASE, \
342 ROMLIB_RW_END - ROMLIB_RW_BASE, \
343 MT_MEMORY | MT_RW | MT_SECURE)
344#endif /* USE_ROMLIB */
345
346/*
347 * Map mem_protect flash region with read and write permissions
348 */
349#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \
350 PLAT_ARM_MEM_PROT_ADDR, \
351 V2M_FLASH_BLOCK_SIZE, \
352 MT_DEVICE | MT_RW | MT_SECURE)
353/*
354 * Map the region for device tree configuration with read and write permissions
355 */
356#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
357 ARM_BL_RAM_BASE, \
358 (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \
359 MT_MEMORY | MT_RW | MT_SECURE)
360
361/*
362 * The max number of regions like RO(code), coherent and data required by
363 * different BL stages which need to be mapped in the MMU.
364 */
365#define ARM_BL_REGIONS 10
366
367#define MAX_MMAP_REGIONS ( \
368 PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
369
370/* Memory mapped Generic timer interfaces */
371#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000)
372
373#define ARM_CONSOLE_BAUDRATE 115200
374
375/*
376 * The TBBR document specifies a watchdog timeout of 256 seconds. SP805
377 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec)
378 */
379#define ARM_TWDG_TIMEOUT_SEC 128
380#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
381 ARM_TWDG_TIMEOUT_SEC)
382
383/******************************************************************************
384 * Required platform porting definitions common to all ARM standard platforms
385 *****************************************************************************/
386
387/*
388 * Some data must be aligned on the biggest cache line size in the platform.
389 * This is known only to the platform as it might have a combination of
390 * integrated and external caches (64 on Arbel).
391 */
392#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
393
394/*
395 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
396 * and limit. Leave enough space of BL2 meminfo.
397 */
398#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
399#define ARM_FW_CONFIG_LIMIT ( \
400 (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U))
401
402/*
403 * Boot parameters passed from BL2 to BL31/BL32 are stored here
404 */
405#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
406#define ARM_BL2_MEM_DESC_LIMIT ( \
407 ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U))
408
409/*
410 * Define limit of firmware configuration memory:
411 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
412 */
413#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
414
415/*******************************************************************************
416 * BL1 specific defines.
417 * BL1 RW data is relocated from ROM to RAM at runtime so we need
418 * two sets of addresses.
419 ******************************************************************************/
420#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
421#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \
422 (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE))
423/*
424 * Put BL1 RW at the top of the Trusted SRAM.
425 */
426#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \
427 (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE))
428#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
429 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
430
431#define ROMLIB_RO_BASE BL1_RO_LIMIT
432#define ROMLIB_RO_LIMIT ( \
433 PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
434
435#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
436#define ROMLIB_RW_END ( \
437 ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
438
439/******************************************************************************
440 * BL2 specific defines.
441 *****************************************************************************/
442#if BL2_AT_EL3
443/* Put BL2 towards the middle of the Trusted SRAM */
444#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
445 PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
446#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
447#else
448/*
449 * Put BL2 just below BL1.
450 */
451#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
452#define BL2_LIMIT BL1_RW_BASE
453#endif /* BL2_AT_EL3 */
454
455/*******************************************************************************
456 * BL31 specific defines.
457 ******************************************************************************/
458#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
459/*
460 * Put BL31 at the bottom of TZC secured DRAM
461 */
462#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
463#define BL31_LIMIT ( \
464 ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE)
465
466/*
467 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
468 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
469 */
470#if SEPARATE_NOBITS_REGION
471#define BL31_NOBITS_BASE BL2_BASE
472#define BL31_NOBITS_LIMIT BL2_LIMIT
473#endif /* SEPARATE_NOBITS_REGION */
474#elif (RESET_TO_BL31)
475/* Ensure Position Independent support (PIE) is enabled for this config.*/
476#if !ENABLE_PIE
477#error "BL31 must be a PIE if RESET_TO_BL31=1."
478#endif /* !ENABLE_PIE */
479/*
480 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
481 * used for building BL31 and not used for loading BL31.
482 */
483#define NEW_SRAM_ALLOCATION
484
485#ifdef NEW_SRAM_ALLOCATION
486 #define BL31_BASE 0x20001000
487#else
488 #define BL31_BASE 0x20001000
489#endif /* NEW_SRAM_ALLOCATION */
490
491#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */
492#else
493/* Put BL31 below BL2 in the Trusted SRAM.*/
494#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \
495 PLAT_ARM_MAX_BL31_SIZE)
496#define BL31_PROGBITS_LIMIT BL2_BASE
497
498/*
499 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE.
500 * This is because in the BL2_AT_EL3 configuration, BL2 is always resident.
501 */
502#if BL2_AT_EL3
503#define BL31_LIMIT BL2_BASE
504#else
505#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
506#endif /* BL2_AT_EL3 */
507#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */
508
509/*
510 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is
511 * no SPD and no SPM-MM, as they are the only ones that can be used as BL32.
512 */
513#if defined(SPD_none) && !SPM_MM
514#undef BL32_BASE
515#endif /* SPD_none && !SPM_MM */
516
517/******************************************************************************
518 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
519 *****************************************************************************/
520#define BL2U_BASE BL2_BASE
521#define BL2U_LIMIT BL2_LIMIT
522
523#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
524#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
525
526/*
527 * ID of the secure physical generic timer interrupt used by the TSP.
528 */
529#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
530
531/*
532 * One cache line needed for bakery locks on ARM platforms
533 */
534#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
535
536/* Priority levels for ARM platforms */
537#define PLAT_RAS_PRI 0x10
538#define PLAT_SDEI_CRITICAL_PRI 0x60
539#define PLAT_SDEI_NORMAL_PRI 0x70
540
541/* ARM platforms use 3 upper bits of secure interrupt priority */
542#define ARM_PRI_BITS 3
543
544/* SGI used for SDEI signalling */
545#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
546
547#if SDEI_IN_FCONF
548/* ARM SDEI dynamic private event max count */
549#define ARM_SDEI_DP_EVENT_MAX_CNT 3
550
551/* ARM SDEI dynamic shared event max count */
552#define ARM_SDEI_DS_EVENT_MAX_CNT 3
553#else
554/* ARM SDEI dynamic private event numbers */
555#define ARM_SDEI_DP_EVENT_0 1000
556#define ARM_SDEI_DP_EVENT_1 1001
557#define ARM_SDEI_DP_EVENT_2 1002
558
559/* ARM SDEI dynamic shared event numbers */
560#define ARM_SDEI_DS_EVENT_0 2000
561#define ARM_SDEI_DS_EVENT_1 2001
562#define ARM_SDEI_DS_EVENT_2 2002
563
564#define ARM_SDEI_PRIVATE_EVENTS \
565 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
566 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
567 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
568 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
569
570#define ARM_SDEI_SHARED_EVENTS \
571 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
572 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
573 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
574#endif /* SDEI_IN_FCONF */
575
576#endif /* ARM_DEF_H */