| Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef HISI_SRAM_MAP_H |
| 8 | #define HISI_SRAM_MAP_H |
| Haojian Zhuang | 934ae71 | 2017-05-24 08:47:49 +0800 | [diff] [blame] | 9 | |
| 10 | /* |
| 11 | * SRAM Memory Region Layout |
| 12 | * |
| 13 | * +-----------------------+ |
| 14 | * | Low Power Mode | 7KB |
| 15 | * +-----------------------+ |
| 16 | * | Secure OS | 64KB |
| 17 | * +-----------------------+ |
| 18 | * | Software Flag | 1KB |
| 19 | * +-----------------------+ |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | #define SOC_SRAM_OFF_BASE_ADDR (0xFFF80000) |
| 24 | |
| 25 | /* PM Section: 7KB */ |
| 26 | #define SRAM_PM_ADDR (SOC_SRAM_OFF_BASE_ADDR) |
| 27 | #define SRAM_PM_SIZE (0x00001C00) |
| 28 | |
| 29 | /* TEE OS Section: 64KB */ |
| 30 | #define SRAM_TEEOS_ADDR (SRAM_PM_ADDR + SRAM_PM_SIZE) |
| 31 | #define SRAM_TEEOS_SIZE (0x00010000) |
| 32 | |
| 33 | /* General Use Section: 1KB */ |
| 34 | #define SRAM_GENERAL_ADDR (SRAM_TEEOS_ADDR + SRAM_TEEOS_SIZE) |
| 35 | #define SRAM_GENERAL_SIZE (0x00000400) |
| 36 | |
| 37 | /* |
| 38 | * General Usage Section Layout: |
| 39 | * |
| 40 | * +-----------------------+ |
| 41 | * | AP boot flag | 64B |
| 42 | * +-----------------------+ |
| 43 | * | DICC flag | 32B |
| 44 | * +-----------------------+ |
| 45 | * | Soft flag | 256B |
| 46 | * +-----------------------+ |
| 47 | * | Thermal flag | 128B |
| 48 | * +-----------------------+ |
| 49 | * | CSHELL | 4B |
| 50 | * +-----------------------+ |
| 51 | * | Uart Switching | 4B |
| 52 | * +-----------------------+ |
| 53 | * | ICC | 1024B |
| 54 | * +-----------------------+ |
| 55 | * | Memory Management | 1024B |
| 56 | * +-----------------------+ |
| 57 | * | IFC | 32B |
| 58 | * +-----------------------+ |
| 59 | * | HIFI | 32B |
| 60 | * +-----------------------+ |
| 61 | * | DDR capacity | 4B |
| 62 | * +-----------------------+ |
| 63 | * | Reserved | |
| 64 | * +-----------------------+ |
| 65 | * |
| 66 | */ |
| 67 | |
| 68 | /* App Core Boot Flags */ |
| 69 | #define MEMORY_AXI_ACPU_START_ADDR (SRAM_GENERAL_ADDR) |
| 70 | #define MEMORY_AXI_ACPU_START_SIZE (64) |
| 71 | |
| 72 | #define MEMORY_AXI_SRESET_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0000) |
| 73 | #define MEMORY_AXI_SECOND_CPU_BOOT_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0004) |
| 74 | #define MEMORY_AXI_READY_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0008) |
| 75 | #define MEMORY_AXI_FASTBOOT_ENTRY_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x000C) |
| 76 | #define MEMORY_AXI_PD_CHARGE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0010) |
| 77 | #define MEMORY_AXI_DBG_ALARM_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0014) |
| 78 | #define MEMORY_AXI_CHIP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0018) |
| 79 | #define MEMORY_AXI_BOARD_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x001C) |
| 80 | #define MEMORY_AXI_BOARD_ID_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0020) |
| 81 | #define MEMORY_AXI_CHARGETYPE_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0024) |
| 82 | #define MEMORY_AXI_COLD_START_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0028) |
| 83 | #define MEMORY_AXI_ANDROID_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x002C) |
| 84 | #define MEMORY_AXI_ACPU_WDTRST_REBOOT_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0030) |
| 85 | #define MEMORY_AXI_ABNRST_BITMAP_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0034) |
| 86 | #define MEMORY_AXI_32K_CLK_TYPE_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x0038) |
| 87 | #define AXI_MODEM_PANIC_FLAG_ADDR (MEMORY_AXI_ACPU_START_ADDR + 0x003C) |
| 88 | #define AXI_MODEM_PANIC_FLAG (0x68697369) |
| 89 | #define MEMORY_AXI_ACPU_END_ADDR (AXI_MODEM_PANIC_FLAG_ADDR + 4) |
| 90 | |
| 91 | /* DICC Flags */ |
| 92 | #define MEMORY_AXI_DICC_ADDR (MEMORY_AXI_ACPU_START_ADDR + MEMORY_AXI_ACPU_START_SIZE) |
| 93 | #define MEMORY_AXI_DICC_SIZE (32) |
| 94 | |
| 95 | #define MEMORY_AXI_SOFT_FLAG_ADDR (MEMORY_AXI_DICC_ADDR + MEMORY_AXI_DICC_SIZE) |
| 96 | #define MEMORY_AXI_SOFT_FLAG_SIZE (256) |
| 97 | |
| 98 | /* Thermal Flags */ |
| 99 | #define MEMORY_AXI_TEMP_PROTECT_ADDR (MEMORY_AXI_SOFT_FLAG_ADDR + MEMORY_AXI_SOFT_FLAG_SIZE) |
| 100 | #define MEMORY_AXI_TEMP_PROTECT_SIZE (128) |
| 101 | |
| 102 | /* CSHELL */ |
| 103 | #define MEMORY_AXI_USB_CSHELL_ADDR (MEMORY_AXI_TEMP_PROTECT_ADDR + MEMORY_AXI_TEMP_PROTECT_SIZE) |
| 104 | #define MEMORY_AXI_USB_CSHELL_SIZE (4) |
| 105 | |
| 106 | /* Uart and A/C Shell Switch Flags */ |
| 107 | #define MEMORY_AXI_UART_INOUT_ADDR (MEMORY_AXI_USB_CSHELL_ADDR + MEMORY_AXI_USB_CSHELL_SIZE) |
| 108 | #define MEMORY_AXI_UART_INOUT_SIZE (4) |
| 109 | |
| 110 | /* IFC Flags */ |
| 111 | #define MEMORY_AXI_IFC_ADDR (MEMORY_AXI_UART_INOUT_ADDR + MEMORY_AXI_UART_INOUT_SIZE) |
| 112 | #define MEMORY_AXI_IFC_SIZE (32) |
| 113 | |
| 114 | /* HIFI Data */ |
| 115 | #define MEMORY_AXI_HIFI_ADDR (MEMORY_AXI_IFC_ADDR + MEMORY_AXI_IFC_SIZE) |
| 116 | #define MEMORY_AXI_HIFI_SIZE (32) |
| 117 | |
| 118 | /* CONFIG Flags */ |
| 119 | #define MEMORY_AXI_CONFIG_ADDR (MEMORY_AXI_HIFI_ADDR + MEMORY_AXI_HIFI_SIZE) |
| 120 | #define MEMORY_AXI_CONFIG_SIZE (32) |
| 121 | |
| 122 | /* DDR Capacity Flags */ |
| 123 | #define MEMORY_AXI_DDR_CAPACITY_ADDR (MEMORY_AXI_CONFIG_ADDR + MEMORY_AXI_CONFIG_SIZE) |
| 124 | #define MEMORY_AXI_DDR_CAPACITY_SIZE (4) |
| 125 | |
| 126 | /* USB Shell Flags */ |
| 127 | #define MEMORY_AXI_USB_SHELL_FLAG_ADDR (MEMORY_AXI_DDR_CAPACITY_ADDR + MEMORY_AXI_DDR_CAPACITY_SIZE) |
| 128 | #define MEMORY_AXI_USB_SHELL_FLAG_SIZE (4) |
| 129 | |
| 130 | /* MCU WDT Switch Flag */ |
| 131 | #define MEMORY_AXI_MCU_WDT_FLAG_ADDR (MEMORY_AXI_USB_SHELL_FLAG_ADDR + MEMORY_AXI_USB_SHELL_FLAG_SIZE) |
| 132 | #define MEMORY_AXI_MCU_WDT_FLAG_SIZE (4) |
| 133 | |
| 134 | /* TLDSP Mailbox MNTN */ |
| 135 | #define SRAM_DSP_MNTN_INFO_ADDR (MEMORY_AXI_MCU_WDT_FLAG_ADDR + MEMORY_AXI_MCU_WDT_FLAG_SIZE) |
| 136 | #define SRAM_DSP_MNTN_SIZE (32) |
| 137 | |
| 138 | /* TLDSP ARM Mailbox Protect Flag */ |
| 139 | #define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR (SRAM_DSP_MNTN_INFO_ADDR + SRAM_DSP_MNTN_SIZE) |
| 140 | #define SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE (4) |
| 141 | |
| 142 | /* RTT Sleep Flag */ |
| 143 | #define SRAM_RTT_SLEEP_FLAG_ADDR (SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_ADDR + SRAM_DSP_ARM_MAILBOX_PROTECT_FLAG_SIZE) |
| 144 | #define SRAM_RTT_SLEEP_FLAG_SIZE (32) |
| 145 | |
| 146 | /* LDSP Awake Flag */ |
| 147 | #define MEMORY_AXI_LDSP_AWAKE_ADDR (SRAM_RTT_SLEEP_FLAG_ADDR + SRAM_RTT_SLEEP_FLAG_SIZE) |
| 148 | #define MEMORY_AXI_LDSP_AWAKE_SIZE (4) |
| 149 | |
| 150 | #define NVUPDATE_SUCCESS 0x5555AAAA |
| 151 | #define NVUPDATE_FAILURE 0xAAAA5555 |
| 152 | |
| 153 | /* |
| 154 | * Low Power Mode Region |
| 155 | */ |
| 156 | #define PWRCTRL_ACPU_ASM_SPACE_ADDR (SRAM_PM_ADDR) |
| 157 | #define PWRCTRL_ACPU_ASM_SPACE_SIZE (SRAM_PM_SIZE) |
| 158 | |
| 159 | #define PWRCTRL_ACPU_ASM_MEM_BASE (PWRCTRL_ACPU_ASM_SPACE_ADDR) |
| 160 | #define PWRCTRL_ACPU_ASM_MEM_SIZE (PWRCTRL_ACPU_ASM_SPACE_SIZE) |
| 161 | #define PWRCTRL_ACPU_ASM_CODE_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0x200) |
| 162 | #define PWRCTRL_ACPU_ASM_DATA_BASE (PWRCTRL_ACPU_ASM_MEM_BASE + 0xE00) |
| 163 | #define PWRCTRL_ACPU_ASM_DATA_SIZE (0xE00) |
| 164 | |
| 165 | #define PWRCTRL_ACPU_ASM_D_C0_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE) |
| 166 | #define PWRCTRL_ACPU_ASM_D_C0_MMU_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0) |
| 167 | #define PWRCTRL_ACPU_ASM_D_ARM_PARA_AD (PWRCTRL_ACPU_ASM_DATA_BASE + 0x20) |
| 168 | |
| 169 | #define PWRCTRL_ACPU_ASM_D_COMM_ADDR (PWRCTRL_ACPU_ASM_DATA_BASE + 0x700) |
| 170 | |
| 171 | #define PWRCTRL_ACPU_REBOOT (PWRCTRL_ACPU_ASM_D_COMM_ADDR) |
| 172 | #define PWRCTRL_ACPU_REBOOT_SIZE (0x200) |
| 173 | #define PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR (PWRCTRL_ACPU_REBOOT + PWRCTRL_ACPU_REBOOT_SIZE) |
| 174 | #define PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE (4) |
| 175 | #define PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR (PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR + PWRCTRL_ACPU_ASM_SLICE_BAK_SIZE) |
| 176 | #define PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE (4) |
| 177 | #define EXCH_A_CORE_POWRCTRL_CONV_ADDR (PWRCTRL_ACPU_ASM_DEBUG_FLAG_ADDR + PWRCTRL_ACPU_ASM_DEBUG_FLAG_SIZE) |
| 178 | #define EXCH_A_CORE_POWRCTRL_CONV_SIZE (4) |
| 179 | |
| 180 | /* |
| 181 | * Below region memory mapping is: |
| 182 | * 4 + 12 + 16 + 28 + 28 + 16 + 28 + 12 + 24 + 20 + 64 + |
| 183 | * 4 + 4 + 4 + 4 + 12 + 4 + 4 + 4 + 4 + 16 + 4 + 0x2BC + |
| 184 | * 24 + 20 + 12 + 16 |
| 185 | */ |
| 186 | |
| 187 | #define MEMORY_AXI_CPU_IDLE_ADDR (EXCH_A_CORE_POWRCTRL_CONV_ADDR + EXCH_A_CORE_POWRCTRL_CONV_SIZE) |
| 188 | #define MEMORY_AXI_CPU_IDLE_SIZE (4) |
| 189 | |
| 190 | #define MEMORY_AXI_CUR_FREQ_ADDR (MEMORY_AXI_CPU_IDLE_ADDR + MEMORY_AXI_CPU_IDLE_SIZE) |
| 191 | #define MEMORY_AXI_CUR_FREQ_SIZE (12) |
| 192 | |
| 193 | #define MEMORY_AXI_ACPU_FREQ_VOL_ADDR (MEMORY_AXI_CUR_FREQ_ADDR + MEMORY_AXI_CUR_FREQ_SIZE) |
| 194 | #define MEMORY_AXI_ACPU_FREQ_VOL_SIZE (16 + 28 + 28) |
| 195 | |
| 196 | #define MEMORY_AXI_DDR_FREQ_VOL_ADDR (MEMORY_AXI_ACPU_FREQ_VOL_ADDR + MEMORY_AXI_ACPU_FREQ_VOL_SIZE) |
| 197 | #define MEMORY_AXI_DDR_FREQ_VOL_SIZE (16 + 28) |
| 198 | |
| 199 | #define MEMORY_AXI_ACPU_FIQ_TEST_ADDR (MEMORY_AXI_DDR_FREQ_VOL_ADDR + MEMORY_AXI_DDR_FREQ_VOL_SIZE) |
| 200 | #define MEMORY_AXI_ACPU_FIQ_TEST_SIZE (12) |
| 201 | |
| 202 | #define MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_TEST_ADDR + MEMORY_AXI_ACPU_FIQ_TEST_SIZE) |
| 203 | #define MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE (24) |
| 204 | |
| 205 | #define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR (MEMORY_AXI_ACPU_FIQ_CPU_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_CPU_INFO_SIZE) |
| 206 | #define MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE (20) |
| 207 | |
| 208 | #define MEMORY_FREQDUMP_ADDR (MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_ADDR + MEMORY_AXI_ACPU_FIQ_DEBUG_INFO_SIZE) |
| 209 | #define MEMORY_FREQDUMP_SIZE (64) |
| 210 | |
| 211 | #define MEMORY_AXI_CCPU_LOG_ADDR (MEMORY_FREQDUMP_ADDR + MEMORY_FREQDUMP_SIZE) |
| 212 | #define MEMORY_AXI_CCPU_LOG_SIZE (4) |
| 213 | |
| 214 | #define MEMORY_AXI_MCU_LOG_ADDR (MEMORY_AXI_CCPU_LOG_ADDR + MEMORY_AXI_CCPU_LOG_SIZE) |
| 215 | #define MEMORY_AXI_MCU_LOG_SIZE (4) |
| 216 | |
| 217 | #define MEMORY_AXI_SEC_CORE_BOOT_ADDR (MEMORY_AXI_MCU_LOG_ADDR + MEMORY_AXI_MCU_LOG_SIZE) |
| 218 | #define MEMORY_AXI_SEC_CORE_BOOT_SIZE (4) |
| 219 | |
| 220 | #define MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR (MEMORY_AXI_SEC_CORE_BOOT_ADDR + MEMORY_AXI_SEC_CORE_BOOT_SIZE) |
| 221 | #define MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE (0x4) |
| 222 | |
| 223 | #define POLICY_AREA_RESERVED (MEMORY_AXI_BBP_PS_VOTE_FLAG_ADDR + MEMORY_AXI_BBP_PS_VOTE_FLAG_SIZE) |
| 224 | #define POLICY_AREA_RESERVED_SIZE (12) |
| 225 | |
| 226 | #define DDR_POLICY_VALID_MAGIC (POLICY_AREA_RESERVED + POLICY_AREA_RESERVED_SIZE) |
| 227 | #define DDR_POLICY_VALID_MAGIC_SIZE (4) |
| 228 | |
| 229 | #define DDR_POLICY_MAX_NUM (DDR_POLICY_VALID_MAGIC + DDR_POLICY_VALID_MAGIC_SIZE) |
| 230 | #define DDR_POLICY_MAX_NUM_SIZE (4) |
| 231 | |
| 232 | #define DDR_POLICY_SUPPORT_NUM (DDR_POLICY_MAX_NUM + DDR_POLICY_MAX_NUM_SIZE) |
| 233 | #define DDR_POLICY_SUPPORT_NUM_SIZE (4) |
| 234 | |
| 235 | #define DDR_POLICY_CUR_POLICY (DDR_POLICY_SUPPORT_NUM + DDR_POLICY_SUPPORT_NUM_SIZE) |
| 236 | #define DDR_POLICY_CUR_POLICY_SIZE (4) |
| 237 | |
| 238 | #define ACPU_POLICY_VALID_MAGIC (DDR_POLICY_CUR_POLICY + DDR_POLICY_CUR_POLICY_SIZE) |
| 239 | #define ACPU_POLICY_VALID_MAGIC_SIZE (4) |
| 240 | |
| 241 | #define ACPU_POLICY_MAX_NUM (ACPU_POLICY_VALID_MAGIC + ACPU_POLICY_VALID_MAGIC_SIZE) |
| 242 | #define ACPU_POLICY_MAX_NUM_SIZE (4) |
| 243 | |
| 244 | #define ACPU_POLICY_SUPPORT_NUM (ACPU_POLICY_MAX_NUM + ACPU_POLICY_MAX_NUM_SIZE) |
| 245 | #define ACPU_POLICY_SUPPORT_NUM_SIZE (4) |
| 246 | |
| 247 | #define ACPU_POLICY_CUR_POLICY (ACPU_POLICY_SUPPORT_NUM + ACPU_POLICY_SUPPORT_NUM_SIZE) |
| 248 | #define ACPU_POLICY_CUR_POLICY_SIZE (4) |
| 249 | |
| 250 | #define LPDDR_OPTION_ADDR (ACPU_POLICY_CUR_POLICY + ACPU_POLICY_CUR_POLICY_SIZE) |
| 251 | #define LPDDR_OPTION_SIZE (4) |
| 252 | |
| 253 | #define MEMORY_AXI_DDR_DDL_ADDR (LPDDR_OPTION_ADDR + LPDDR_OPTION_SIZE) |
| 254 | #define MEMORY_AXI_DDR_DDL_SIZE (0x2BC) |
| 255 | |
| 256 | #define DDR_TEST_DFS_ADDR (MEMORY_AXI_DDR_DDL_ADDR + MEMORY_AXI_DDR_DDL_SIZE) |
| 257 | #define DDR_TEST_DFS_ADDR_SIZE (4) |
| 258 | |
| 259 | #define DDR_TEST_DFS_TIMES_ADDR (DDR_TEST_DFS_ADDR + DDR_TEST_DFS_ADDR_SIZE) |
| 260 | #define DDR_TEST_DFS_TIMES_ADDR_SIZE (4) |
| 261 | |
| 262 | #define DDR_TEST_QOS_ADDR (DDR_TEST_DFS_TIMES_ADDR + DDR_TEST_DFS_TIMES_ADDR_SIZE) |
| 263 | #define DDR_TEST_QOS_ADDR_SIZE (4) |
| 264 | |
| 265 | #define DDR_TEST_FUN_ADDR (DDR_TEST_QOS_ADDR + DDR_TEST_QOS_ADDR_SIZE) |
| 266 | #define DDR_TEST_FUN_ADDR_SIZE (4) |
| 267 | |
| 268 | #define BOARD_TYPE_ADDR (DDR_TEST_FUN_ADDR + DDR_TEST_FUN_ADDR_SIZE) |
| 269 | #define BOARD_ADDR_SIZE (4) |
| 270 | #define DDR_DFS_FREQ_ADDR (BOARD_TYPE_ADDR + BOARD_ADDR_SIZE) |
| 271 | #define DDR_DFS_FREQ_SIZE (4) |
| 272 | |
| 273 | #define DDR_PASR_ADDR (DDR_DFS_FREQ_ADDR + DDR_DFS_FREQ_SIZE) |
| 274 | #define DDR_PASR_SIZE (20) |
| 275 | |
| 276 | #define ACPU_DFS_FREQ_ADDR (DDR_PASR_ADDR + DDR_PASR_SIZE) |
| 277 | #define ACPU_DFS_FREQ_ADDR_SIZE (12) |
| 278 | |
| 279 | #define ACPU_CHIP_MAX_FREQ (ACPU_DFS_FREQ_ADDR + ACPU_DFS_FREQ_ADDR_SIZE) |
| 280 | #define ACPU_CHIP_MAX_FREQ_SIZE (4) |
| 281 | |
| 282 | #define MEMORY_MEDPLL_STATE_ADDR (ACPU_CHIP_MAX_FREQ + ACPU_CHIP_MAX_FREQ_SIZE) |
| 283 | #define MEMORY_MEDPLL_STATE_SIZE (8) |
| 284 | |
| 285 | #define MEMORY_CCPU_LOAD_FLAG_ADDR (MEMORY_MEDPLL_STATE_ADDR + MEMORY_MEDPLL_STATE_SIZE) |
| 286 | #define MEMORY_CCPU_LOAD_FLAG_SIZE (4) |
| 287 | |
| 288 | |
| 289 | #define ACPU_CORE_BITS_ADDR (MEMORY_CCPU_LOAD_FLAG_ADDR + MEMORY_CCPU_LOAD_FLAG_SIZE) |
| 290 | #define ACPU_CORE_BITS_SIZE (4) |
| 291 | |
| 292 | #define ACPU_CLUSTER_IDLE_ADDR (ACPU_CORE_BITS_ADDR + ACPU_CORE_BITS_SIZE) |
| 293 | #define ACPU_CLUSTER_IDLE_SIZE (4) |
| 294 | |
| 295 | #define ACPU_A53_FLAGS_ADDR (ACPU_CLUSTER_IDLE_ADDR + ACPU_CLUSTER_IDLE_SIZE) |
| 296 | #define ACPU_A53_FLAGS_SIZE (4) |
| 297 | |
| 298 | #define ACPU_POWER_STATE_QOS_ADDR (ACPU_A53_FLAGS_ADDR+ACPU_A53_FLAGS_SIZE) |
| 299 | #define ACPU_POWER_STATE_QOS_SIZE (4) |
| 300 | |
| 301 | #define ACPU_UNLOCK_CORE_FLAGS_ADDR (ACPU_POWER_STATE_QOS_ADDR+ACPU_POWER_STATE_QOS_SIZE) |
| 302 | #define ACPU_UNLOCK_CORE_FLAGS_SIZE (8) |
| 303 | |
| 304 | #define ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR (ACPU_UNLOCK_CORE_FLAGS_ADDR + ACPU_UNLOCK_CORE_FLAGS_SIZE) |
| 305 | #define ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE (4) |
| 306 | |
| 307 | #define ACPU_CORE_POWERDOWN_FLAGS_ADDR (ACPU_SUBSYS_POWERDOWN_FLAGS_ADDR + ACPU_SUBSYS_POWERDOWN_FLAGS_SIZE) |
| 308 | #define ACPU_CORE_POWERDOWN_FLAGS_SIZE (4) |
| 309 | |
| 310 | #define ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR (ACPU_CORE_POWERDOWN_FLAGS_ADDR + ACPU_CORE_POWERDOWN_FLAGS_SIZE) |
| 311 | #define ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE (4) |
| 312 | |
| 313 | #define ACPU_ARM64_FLAGA (ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR + ACPU_CLUSTER_POWERDOWN_FLAGS_SIZE) |
| 314 | #define ACPU_ARM64_FLAGA_SIZE (4) |
| 315 | |
| 316 | #define ACPU_ARM64_FLAGB (ACPU_ARM64_FLAGA + ACPU_ARM64_FLAGA_SIZE) |
| 317 | #define ACPU_ARM64_FLAGB_SIZE (4) |
| 318 | |
| 319 | #define MCU_EXCEPTION_FLAGS_ADDR (ACPU_ARM64_FLAGB + ACPU_ARM64_FLAGB_SIZE) |
| 320 | #define MCU_EXCEPTION_FLAGS_SIZE (4) |
| 321 | |
| 322 | #define ACPU_MASTER_CORE_STATE_ADDR (MCU_EXCEPTION_FLAGS_ADDR + MCU_EXCEPTION_FLAGS_SIZE) |
| 323 | #define ACPU_MASTER_CORE_STATE_SIZE (4) |
| 324 | |
| 325 | #define PWRCTRL_AXI_RESERVED_ADDR (ACPU_MASTER_CORE_STATE_ADDR + ACPU_MASTER_CORE_STATE_SIZE) |
| 326 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 327 | #endif /* HISI_SRAM_MAP_H */ |