blob: 6a6979c9c3a5eef1d024ab445368b82730f4ac07 [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Sathees Balya50905c72018-10-05 13:30:59 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Sathees Balya50905c72018-10-05 13:30:59 +01006#ifndef V2M_DEF_H
7#define V2M_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +00009#include <lib/utils_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000010
11/* V2M motherboard system registers & offsets */
Sathees Balya50905c72018-10-05 13:30:59 +010012#define V2M_SYSREGS_BASE UL(0x1c010000)
13#define V2M_SYS_ID UL(0x0)
14#define V2M_SYS_SWITCH UL(0x4)
15#define V2M_SYS_LED UL(0x8)
16#define V2M_SYS_NVFLAGS UL(0x38)
17#define V2M_SYS_NVFLAGSSET UL(0x38)
18#define V2M_SYS_NVFLAGSCLR UL(0x3c)
19#define V2M_SYS_CFGDATA UL(0xa0)
20#define V2M_SYS_CFGCTRL UL(0xa4)
21#define V2M_SYS_CFGSTATUS UL(0xa8)
Dan Handley9df48042015-03-19 18:58:55 +000022
Sathees Balya50905c72018-10-05 13:30:59 +010023#define V2M_CFGCTRL_START BIT_32(31)
24#define V2M_CFGCTRL_RW BIT_32(30)
Dan Handley9df48042015-03-19 18:58:55 +000025#define V2M_CFGCTRL_FUNC_SHIFT 20
Sathees Balya50905c72018-10-05 13:30:59 +010026#define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT)
27#define V2M_FUNC_CLK_GEN U(0x01)
28#define V2M_FUNC_TEMP U(0x04)
29#define V2M_FUNC_DB_RESET U(0x05)
30#define V2M_FUNC_SCC_CFG U(0x06)
31#define V2M_FUNC_SHUTDOWN U(0x08)
32#define V2M_FUNC_REBOOT U(0x09)
Dan Handley9df48042015-03-19 18:58:55 +000033
Sathees Balya22576072018-09-03 17:41:13 +010034/* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */
35 #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS)
36
Dan Handley9df48042015-03-19 18:58:55 +000037/*
38 * V2M sysled bit definitions. The values written to this
39 * register are defined in arch.h & runtime_svc.h. Only
40 * used by the primary cpu to diagnose any cold boot issues.
41 *
42 * SYS_LED[0] - Security state (S=0/NS=1)
43 * SYS_LED[2:1] - Exception Level (EL3-EL0)
44 * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
45 *
46 */
47#define V2M_SYS_LED_SS_SHIFT 0x0
48#define V2M_SYS_LED_EL_SHIFT 0x1
49#define V2M_SYS_LED_EC_SHIFT 0x3
50
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000051#define V2M_SYS_LED_SS_MASK U(0x1)
52#define V2M_SYS_LED_EL_MASK U(0x3)
53#define V2M_SYS_LED_EC_MASK U(0x1f)
Dan Handley9df48042015-03-19 18:58:55 +000054
55/* V2M sysid register bits */
56#define V2M_SYS_ID_REV_SHIFT 28
57#define V2M_SYS_ID_HBI_SHIFT 16
58#define V2M_SYS_ID_BLD_SHIFT 12
59#define V2M_SYS_ID_ARCH_SHIFT 8
60#define V2M_SYS_ID_FPGA_SHIFT 0
61
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000062#define V2M_SYS_ID_REV_MASK U(0xf)
63#define V2M_SYS_ID_HBI_MASK U(0xfff)
64#define V2M_SYS_ID_BLD_MASK U(0xf)
65#define V2M_SYS_ID_ARCH_MASK U(0xf)
66#define V2M_SYS_ID_FPGA_MASK U(0xff)
Dan Handley9df48042015-03-19 18:58:55 +000067
68#define V2M_SYS_ID_BLD_LENGTH 4
69
70
71/* NOR Flash */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000072#define V2M_FLASH0_BASE UL(0x08000000)
73#define V2M_FLASH0_SIZE UL(0x04000000)
74#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
Dan Handley9df48042015-03-19 18:58:55 +000075
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000076#define V2M_IOFPGA_BASE UL(0x1c000000)
77#define V2M_IOFPGA_SIZE UL(0x03000000)
Dan Handley9df48042015-03-19 18:58:55 +000078
79/* PL011 UART related constants */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000080#define V2M_IOFPGA_UART0_BASE UL(0x1c090000)
81#define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000)
82#define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000)
83#define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000)
Dan Handley9df48042015-03-19 18:58:55 +000084
85#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
86#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
87#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000
88#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
89
Ryan Harkinf96fc8f2015-03-17 14:54:01 +000090/* SP804 timer related constants */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000091#define V2M_SP804_TIMER0_BASE UL(0x1C110000)
92#define V2M_SP804_TIMER1_BASE UL(0x1C120000)
Dan Handley9df48042015-03-19 18:58:55 +000093
Juan Castillofd383b42015-12-01 16:10:15 +000094/* SP810 controller */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000095#define V2M_SP810_BASE UL(0x1c020000)
96#define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
97#define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
98#define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
99#define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
Juan Castillofd383b42015-12-01 16:10:15 +0000100
Sandrine Bailleux889ca032016-06-14 17:01:00 +0100101/*
102 * The flash can be mapped either as read-only or read-write.
103 *
104 * If it is read-write then it should also be mapped as device memory because
105 * NOR flash programming involves sending a fixed, ordered sequence of commands.
106 *
107 * If it is read-only then it should also be mapped as:
108 * - Normal memory, because reading from NOR flash is transparent, it is like
109 * reading from RAM.
110 * - Non-executable by default. If some parts of the flash need to be executable
111 * then platform code is responsible for re-mapping the appropriate portion
112 * of it as executable.
113 */
Juan Castillob6132f12015-10-06 14:01:35 +0100114#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
115 V2M_FLASH0_SIZE, \
116 MT_DEVICE | MT_RW | MT_SECURE)
117
118#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
Dan Handley9df48042015-03-19 18:58:55 +0000119 V2M_FLASH0_SIZE, \
Sandrine Bailleux889ca032016-06-14 17:01:00 +0100120 MT_RO_DATA | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000121
122#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
123 V2M_IOFPGA_SIZE, \
124 MT_DEVICE | MT_RW | MT_SECURE)
125
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000126/* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */
127#define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \
128 V2M_IOFPGA_BASE, \
129 V2M_IOFPGA_SIZE, \
130 MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
Dan Handley9df48042015-03-19 18:58:55 +0000131
132
Sathees Balya50905c72018-10-05 13:30:59 +0100133#endif /* V2M_DEF_H */