Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 31 | #include <asm_macros.S> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 32 | #include <cortex_a53.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 33 | #include <cpu_macros.S> |
| 34 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 36 | /* --------------------------------------------- |
| 37 | * Disable L1 data cache and unified L2 cache |
| 38 | * --------------------------------------------- |
| 39 | */ |
| 40 | func cortex_a53_disable_dcache |
| 41 | mrs x1, sctlr_el3 |
| 42 | bic x1, x1, #SCTLR_C_BIT |
| 43 | msr sctlr_el3, x1 |
| 44 | isb |
| 45 | ret |
| 46 | |
| 47 | /* --------------------------------------------- |
| 48 | * Disable intra-cluster coherency |
| 49 | * --------------------------------------------- |
| 50 | */ |
| 51 | func cortex_a53_disable_smp |
| 52 | mrs x0, CPUECTLR_EL1 |
| 53 | bic x0, x0, #CPUECTLR_SMP_BIT |
| 54 | msr CPUECTLR_EL1, x0 |
| 55 | isb |
| 56 | dsb sy |
| 57 | ret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 59 | func cortex_a53_reset_func |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | /* --------------------------------------------- |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 61 | * As a bare minimum enable the SMP bit. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | * --------------------------------------------- |
| 63 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 64 | mrs x0, CPUECTLR_EL1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | orr x0, x0, #CPUECTLR_SMP_BIT |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 66 | msr CPUECTLR_EL1, x0 |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 67 | isb |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 68 | ret |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 69 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 70 | func cortex_a53_core_pwr_dwn |
| 71 | mov x18, x30 |
| 72 | |
| 73 | /* --------------------------------------------- |
| 74 | * Turn off caches. |
| 75 | * --------------------------------------------- |
| 76 | */ |
| 77 | bl cortex_a53_disable_dcache |
| 78 | |
| 79 | /* --------------------------------------------- |
| 80 | * Flush L1 cache to PoU. |
| 81 | * --------------------------------------------- |
| 82 | */ |
| 83 | mov x0, #DCCISW |
| 84 | bl dcsw_op_louis |
| 85 | |
| 86 | /* --------------------------------------------- |
| 87 | * Come out of intra cluster coherency |
| 88 | * --------------------------------------------- |
| 89 | */ |
| 90 | mov x30, x18 |
| 91 | b cortex_a53_disable_smp |
| 92 | |
| 93 | func cortex_a53_cluster_pwr_dwn |
| 94 | mov x18, x30 |
| 95 | |
| 96 | /* --------------------------------------------- |
| 97 | * Turn off caches. |
| 98 | * --------------------------------------------- |
| 99 | */ |
| 100 | bl cortex_a53_disable_dcache |
| 101 | |
| 102 | /* --------------------------------------------- |
| 103 | * Disable the optional ACP. |
| 104 | * --------------------------------------------- |
| 105 | */ |
| 106 | bl plat_disable_acp |
| 107 | |
| 108 | /* --------------------------------------------- |
| 109 | * Flush L1 and L2 caches to PoC. |
| 110 | * --------------------------------------------- |
| 111 | */ |
| 112 | mov x0, #DCCISW |
| 113 | bl dcsw_op_all |
| 114 | |
| 115 | /* --------------------------------------------- |
| 116 | * Come out of intra cluster coherency |
| 117 | * --------------------------------------------- |
| 118 | */ |
| 119 | mov x30, x18 |
| 120 | b cortex_a53_disable_smp |
| 121 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 122 | /* --------------------------------------------- |
| 123 | * This function provides cortex_a53 specific |
| 124 | * register information for crash reporting. |
| 125 | * It needs to return with x6 pointing to |
| 126 | * a list of register names in ascii and |
| 127 | * x8 - x15 having values of registers to be |
| 128 | * reported. |
| 129 | * --------------------------------------------- |
| 130 | */ |
| 131 | .section .rodata.cortex_a53_regs, "aS" |
| 132 | cortex_a53_regs: /* The ascii list of register names to be reported */ |
| 133 | .asciz "cpuectlr_el1", "" |
| 134 | |
| 135 | func cortex_a53_cpu_reg_dump |
| 136 | adr x6, cortex_a53_regs |
| 137 | mrs x8, CPUECTLR_EL1 |
| 138 | ret |
| 139 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 140 | declare_cpu_ops cortex_a53, CORTEX_A53_MIDR |