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Rajan Vaja5529a012018-01-17 02:39:23 -08001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * ZynqMP system level PM-API functions for pin control.
9 */
10
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000011#ifndef PM_API_IOCTL_H
12#define PM_API_IOCTL_H
Rajan Vaja5529a012018-01-17 02:39:23 -080013
14#include "pm_common.h"
15
Jolly Shah69fb5bf2018-02-07 16:25:41 -080016//ioctl id
17enum {
Ronak Jain26a8bb22021-06-27 22:31:20 -070018 IOCTL_GET_RPU_OPER_MODE = 0,
19 IOCTL_SET_RPU_OPER_MODE = 1,
20 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
21 IOCTL_TCM_COMB_CONFIG = 3,
22 IOCTL_SET_TAPDELAY_BYPASS = 4,
23 IOCTL_SET_SGMII_MODE = 5,
24 IOCTL_SD_DLL_RESET = 6,
25 IOCTL_SET_SD_TAPDELAY = 7,
Rajan Vaja35116132018-01-17 02:39:25 -080026 /* Ioctl for clock driver */
Ronak Jain26a8bb22021-06-27 22:31:20 -070027 IOCTL_SET_PLL_FRAC_MODE = 8,
28 IOCTL_GET_PLL_FRAC_MODE = 9,
29 IOCTL_SET_PLL_FRAC_DATA = 10,
30 IOCTL_GET_PLL_FRAC_DATA = 11,
31 IOCTL_WRITE_GGS = 12,
32 IOCTL_READ_GGS = 13,
33 IOCTL_WRITE_PGGS = 14,
34 IOCTL_READ_PGGS = 15,
Siva Durga Prasad Paladugued1d5cb2018-09-04 17:03:25 +053035 /* IOCTL for ULPI reset */
Ronak Jain26a8bb22021-06-27 22:31:20 -070036 IOCTL_ULPI_RESET = 16,
Siva Durga Prasad Paladuguac8526f2018-09-04 17:12:51 +053037 /* Set healthy bit value */
Ronak Jain26a8bb22021-06-27 22:31:20 -070038 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
39 IOCTL_AFI = 18,
40 /* Probe counter read/write */
41 IOCTL_PROBE_COUNTER_READ = 19,
42 IOCTL_PROBE_COUNTER_WRITE = 20,
43 IOCTL_OSPI_MUX_SELECT = 21,
44 /* IOCTL for USB power request */
45 IOCTL_USB_SET_STATE = 22,
46 /* IOCTL to get last reset reason */
47 IOCTL_GET_LAST_RESET_REASON = 23,
48 /* AI engine NPI ISR clear */
49 IOCTL_AIE_ISR_CLEAR = 24,
50 /* Register SGI to ATF */
51 IOCTL_REGISTER_SGI = 25,
Ronak Jain42d6f392021-08-11 00:26:28 -070052 /* Runtime feature configuration */
53 IOCTL_SET_FEATURE_CONFIG = 26,
54 IOCTL_GET_FEATURE_CONFIG = 27,
Rajan Vaja5529a012018-01-17 02:39:23 -080055};
56
Jolly Shah69fb5bf2018-02-07 16:25:41 -080057//RPU operation mode
58#define PM_RPU_MODE_LOCKSTEP 0U
59#define PM_RPU_MODE_SPLIT 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080060
Jolly Shah69fb5bf2018-02-07 16:25:41 -080061//RPU boot mem
62#define PM_RPU_BOOTMEM_LOVEC 0U
63#define PM_RPU_BOOTMEM_HIVEC 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080064
Jolly Shah69fb5bf2018-02-07 16:25:41 -080065//RPU tcm mpde
66#define PM_RPU_TCM_SPLIT 0U
67#define PM_RPU_TCM_COMB 1U
Rajan Vaja5529a012018-01-17 02:39:23 -080068
Jolly Shah69fb5bf2018-02-07 16:25:41 -080069//tap delay signal type
70#define PM_TAPDELAY_NAND_DQS_IN 0U
71#define PM_TAPDELAY_NAND_DQS_OUT 1U
72#define PM_TAPDELAY_QSPI 2U
73#define PM_TAPDELAY_MAX 3U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080074
Jolly Shah69fb5bf2018-02-07 16:25:41 -080075//tap delay bypass
76#define PM_TAPDELAY_BYPASS_DISABLE 0U
77#define PM_TAPDELAY_BYPASS_ENABLE 1U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080078
Jolly Shah69fb5bf2018-02-07 16:25:41 -080079//sgmii mode
80#define PM_SGMII_DISABLE 0U
81#define PM_SGMII_ENABLE 1U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080082
83enum tap_delay_type {
84 PM_TAPDELAY_INPUT,
85 PM_TAPDELAY_OUTPUT,
86};
87
Jolly Shah69fb5bf2018-02-07 16:25:41 -080088//dll reset type
89#define PM_DLL_RESET_ASSERT 0U
90#define PM_DLL_RESET_RELEASE 1U
91#define PM_DLL_RESET_PULSE 2U
Rajan Vajaaea41bb2018-01-17 02:39:24 -080092
Rajan Vaja5529a012018-01-17 02:39:23 -080093enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
94 unsigned int ioctl_id,
95 unsigned int arg1,
96 unsigned int arg2,
97 unsigned int *value);
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000098#endif /* PM_API_IOCTL_H */