Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 1 | /* |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a77.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 24 | /* -------------------------------------------------- |
| 25 | * Errata Workaround for Cortex A77 Errata #1800714. |
| 26 | * This applies to revision <= r1p1 of Cortex A77. |
| 27 | * Inputs: |
| 28 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 29 | * Shall clobber: x0-x17 |
| 30 | * -------------------------------------------------- |
| 31 | */ |
| 32 | func errata_a77_1800714_wa |
| 33 | /* Compare x0 against revision <= r1p1 */ |
| 34 | mov x17, x30 |
| 35 | bl check_errata_1800714 |
| 36 | cbz x0, 1f |
| 37 | |
| 38 | /* Disable allocation of splintered pages in the L2 TLB */ |
| 39 | mrs x1, CORTEX_A77_CPUECTLR_EL1 |
| 40 | orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 |
| 41 | msr CORTEX_A77_CPUECTLR_EL1, x1 |
| 42 | isb |
| 43 | 1: |
| 44 | ret x17 |
| 45 | endfunc errata_a77_1800714_wa |
| 46 | |
| 47 | func check_errata_1800714 |
| 48 | /* Applies to everything <= r1p1 */ |
| 49 | mov x1, #0x11 |
| 50 | b cpu_rev_var_ls |
| 51 | endfunc check_errata_1800714 |
| 52 | |
| 53 | /* ------------------------------------------------- |
| 54 | * The CPU Ops reset function for Cortex-A77. |
| 55 | * Shall clobber: x0-x19 |
| 56 | * ------------------------------------------------- |
| 57 | */ |
| 58 | func cortex_a77_reset_func |
| 59 | mov x19, x30 |
| 60 | bl cpu_get_rev_var |
| 61 | mov x18, x0 |
| 62 | |
| 63 | #if ERRATA_A77_1800714 |
| 64 | mov x0, x18 |
| 65 | bl errata_a77_1800714_wa |
| 66 | #endif |
| 67 | |
| 68 | ret x19 |
| 69 | endfunc cortex_a77_reset_func |
| 70 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 71 | /* --------------------------------------------- |
| 72 | * HW will do the cache maintenance while powering down |
| 73 | * --------------------------------------------- |
| 74 | */ |
| 75 | func cortex_a77_core_pwr_dwn |
| 76 | /* --------------------------------------------- |
| 77 | * Enable CPU power down bit in power control register |
| 78 | * --------------------------------------------- |
| 79 | */ |
| 80 | mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 |
| 81 | orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 82 | msr CORTEX_A77_CPUPWRCTLR_EL1, x0 |
| 83 | isb |
| 84 | ret |
| 85 | endfunc cortex_a77_core_pwr_dwn |
| 86 | |
| 87 | #if REPORT_ERRATA |
| 88 | /* |
| 89 | * Errata printing function for Cortex-A77. Must follow AAPCS. |
| 90 | */ |
| 91 | func cortex_a77_errata_report |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 92 | stp x8, x30, [sp, #-16]! |
| 93 | |
| 94 | bl cpu_get_rev_var |
| 95 | mov x8, x0 |
| 96 | |
| 97 | /* |
| 98 | * Report all errata. The revision-variant information is passed to |
| 99 | * checking functions of each errata. |
| 100 | */ |
| 101 | report_errata ERRATA_A77_1800714, cortex_a77, 1800714 |
| 102 | |
| 103 | ldp x8, x30, [sp], #16 |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 104 | ret |
| 105 | endfunc cortex_a77_errata_report |
| 106 | #endif |
| 107 | |
| 108 | |
| 109 | /* --------------------------------------------- |
| 110 | * This function provides Cortex-A77 specific |
| 111 | * register information for crash reporting. |
| 112 | * It needs to return with x6 pointing to |
| 113 | * a list of register names in ascii and |
| 114 | * x8 - x15 having values of registers to be |
| 115 | * reported. |
| 116 | * --------------------------------------------- |
| 117 | */ |
| 118 | .section .rodata.cortex_a77_regs, "aS" |
| 119 | cortex_a77_regs: /* The ascii list of register names to be reported */ |
| 120 | .asciz "cpuectlr_el1", "" |
| 121 | |
| 122 | func cortex_a77_cpu_reg_dump |
| 123 | adr x6, cortex_a77_regs |
| 124 | mrs x8, CORTEX_A77_CPUECTLR_EL1 |
| 125 | ret |
| 126 | endfunc cortex_a77_cpu_reg_dump |
| 127 | |
| 128 | declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 129 | cortex_a77_reset_func, \ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 130 | cortex_a77_core_pwr_dwn |