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git01.mediatek.com / filogic / atf / dd3f0a8f2cdad8dbae116e73bb90e128c14de201 / . / plat / marvell / common / mrvl_sip_svc.c
blob: ec293afa3ec64e09f35c66dc5cc0137b385ff625 [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#include <ap_setup.h>
9#include <cache_llc.h>
10#include <debug.h>
11#include <marvell_plat_priv.h>
12#include <runtime_svc.h>
13#include <smcc.h>
14#include "comphy/phy-comphy-cp110.h"
15
16/* #define DEBUG_COMPHY */
17#ifdef DEBUG_COMPHY
18#define debug(format...) NOTICE(format)
19#else
20#define debug(format, arg...)
21#endif
22
23/* Comphy related FID's */
24#define MV_SIP_COMPHY_POWER_ON 0x82000001
25#define MV_SIP_COMPHY_POWER_OFF 0x82000002
26#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
27#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
28#define MV_SIP_COMPHY_DIG_RESET 0x82000005
29
30/* Miscellaneous FID's' */
31#define MV_SIP_DRAM_SIZE 0x82000010
32#define MV_SIP_LLC_ENABLE 0x82000011
33
34#define MAX_LANE_NR 6
35#define MVEBU_COMPHY_OFFSET 0x441000
36#define MVEBU_SD_OFFSET 0x120000
37
38/* This macro is used to identify COMPHY related calls from SMC function ID */
39#define is_comphy_fid(fid) \
40 ((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
41
42
43uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
44 u_register_t x1,
45 u_register_t x2,
46 u_register_t x3,
47 u_register_t x4,
48 void *cookie,
49 void *handle,
50 u_register_t flags)
51{
52 u_register_t ret;
53 int i;
54
55 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
56 __func__, smc_fid, x1, x2, x3);
57 if (is_comphy_fid(smc_fid)) {
58
59 /* some systems passes SD phys address instead of COMPHY phys
60 * address - convert it
61 */
62 if (x1 & MVEBU_SD_OFFSET)
63 x1 = (x1 & ~0xffffff) + MVEBU_COMPHY_OFFSET;
64
65 if ((x1 & 0xffffff) != MVEBU_COMPHY_OFFSET) {
66 ERROR("%s: Wrong smc (0x%x) address: %lx\n",
67 __func__, smc_fid, x1);
68 SMC_RET1(handle, SMC_UNK);
69 }
70
71 if (x2 >= MAX_LANE_NR) {
72 ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n",
73 __func__, smc_fid, x2);
74 SMC_RET1(handle, SMC_UNK);
75 }
76 }
77
78 switch (smc_fid) {
79
80 /* Comphy related FID's */
81 case MV_SIP_COMPHY_POWER_ON:
82 /* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
83 ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
84 SMC_RET1(handle, ret);
85 case MV_SIP_COMPHY_POWER_OFF:
86 /* x1: comphy_base, x2: comphy_index */
87 ret = mvebu_cp110_comphy_power_off(x1, x2);
88 SMC_RET1(handle, ret);
89 case MV_SIP_COMPHY_PLL_LOCK:
90 /* x1: comphy_base, x2: comphy_index */
91 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2);
92 SMC_RET1(handle, ret);
93 case MV_SIP_COMPHY_XFI_TRAIN:
94 /* x1: comphy_base, x2: comphy_index */
95 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2);
96 SMC_RET1(handle, ret);
97 case MV_SIP_COMPHY_DIG_RESET:
98 /* x1: comphy_base, x2: comphy_index, x3: mode, x4: command */
99 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4);
100 SMC_RET1(handle, ret);
101
102 /* Miscellaneous FID's' */
103 case MV_SIP_DRAM_SIZE:
104 /* x1: ap_base_addr */
105 ret = mvebu_get_dram_size(x1);
106 SMC_RET1(handle, ret);
107 case MV_SIP_LLC_ENABLE:
108 for (i = 0; i < ap_get_count(); i++)
109 llc_runtime_enable(i);
110
111 SMC_RET1(handle, 0);
112
113 default:
114 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
115 SMC_RET1(handle, SMC_UNK);
116 }
117}
118
119/* Define a runtime service descriptor for fast SMC calls */
120DECLARE_RT_SVC(
121 marvell_sip_svc,
122 OEN_SIP_START,
123 OEN_SIP_END,
124 SMC_TYPE_FAST,
125 NULL,
126 mrvl_sip_smc_handler
127);