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Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00005 */
6
7#ifndef __XLAT_TABLES_DEFS_H__
8#define __XLAT_TABLES_DEFS_H__
9
Isla Mitchell02c63072017-07-21 14:44:36 +010010#include <arch.h>
Scott Brandenbf404c02017-04-10 11:45:52 -070011#include <utils_def.h>
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000012
13/* Miscellaneous MMU related constants */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070014#define NUM_2MB_IN_GB (U(1) << 9)
15#define NUM_4K_IN_2MB (U(1) << 9)
16#define NUM_GB_IN_4GB (U(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000017
Varun Wadekarc6a11f62017-05-25 18:04:48 -070018#define TWO_MB_SHIFT U(21)
19#define ONE_GB_SHIFT U(30)
20#define FOUR_KB_SHIFT U(12)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000021
22#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
23#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
24#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
25
Varun Wadekarc6a11f62017-05-25 18:04:48 -070026#define INVALID_DESC U(0x0)
27#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
28#define TABLE_DESC U(0x3) /* Table levels 0-2 */
29#define PAGE_DESC U(0x3) /* Table level 3 */
30#define DESC_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000031
32#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
33#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
34#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
35
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010036/* XN: Translation regimes that support one VA range (EL2 and EL3). */
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000037#define XN (ULL(1) << 2)
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010038/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
39#define UXN (ULL(1) << 2)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000040#define PXN (ULL(1) << 1)
41#define CONT_HINT (ULL(1) << 0)
42#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
43
Varun Wadekarc6a11f62017-05-25 18:04:48 -070044#define NON_GLOBAL (U(1) << 9)
45#define ACCESS_FLAG (U(1) << 8)
46#define NSH (U(0x0) << 6)
47#define OSH (U(0x2) << 6)
48#define ISH (U(0x3) << 6)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000049
50#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
51
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010052/*
53 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
54 * 64KB. However, TF only supports the 4KB case at the moment.
55 */
56#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
Varun Wadekarc6a11f62017-05-25 18:04:48 -070057#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000058#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
59#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
60
Varun Wadekarc6a11f62017-05-25 18:04:48 -070061#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
62#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000063
64#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070065#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000066
Varun Wadekarc6a11f62017-05-25 18:04:48 -070067#define XLAT_TABLE_LEVEL_MAX U(3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000068
69/* Values for number of entries in each MMU translation table */
70#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070071#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000072#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
73
74/* Values to convert a memory address to an index into a translation table */
75#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
76#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
77#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
78#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
79#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
80 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
81
82#define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
83/* Mask to get the bits used to index inside a block of a certain level */
84#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1)
85/* Mask to get the address bits common to a block of a certain table level*/
86#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
87
88/*
89 * AP[1] bit is ignored by hardware and is
90 * treated as if it is One in EL2/EL3
91 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070092#define AP_RO (U(0x1) << 5)
93#define AP_RW (U(0x0) << 5)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000094
Varun Wadekarc6a11f62017-05-25 18:04:48 -070095#define NS (U(0x1) << 3)
96#define ATTR_NON_CACHEABLE_INDEX U(0x2)
97#define ATTR_DEVICE_INDEX U(0x1)
98#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0)
99#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
Isla Mitchell02c63072017-07-21 14:44:36 +0100100
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000101/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
Isla Mitchell02c63072017-07-21 14:44:36 +0100102#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000103/* Device-nGnRE */
Isla Mitchell02c63072017-07-21 14:44:36 +0100104#define ATTR_DEVICE MAIR_DEV_nGnRE
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000105/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
Isla Mitchell02c63072017-07-21 14:44:36 +0100106#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000107#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700108#define ATTR_INDEX_MASK U(0x3)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000109#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
110
111/*
112 * Flags to override default values used to program system registers while
113 * enabling the MMU.
114 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700115#define DISABLE_DCACHE (U(1) << 0)
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000116
Summer Qindaf5dbb2017-03-16 17:16:34 +0000117/*
118 * This flag marks the translation tables are Non-cacheable for MMU accesses.
119 * If the flag is not specified, by default the tables are cacheable.
120 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700121#define XLAT_TABLE_NC (U(1) << 1)
Summer Qindaf5dbb2017-03-16 17:16:34 +0000122
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +0000123#endif /* __XLAT_TABLES_DEFS_H__ */