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git01.mediatek.com / filogic / atf / dc358b250ba55fd1e184eda0f43488f4b462a269 / . / plat / mediatek / mt8192 / drivers / dcm / mtk_dcm_utils.c
blob: 15a700c2b7e58b3f1775ebff479ae32a9c51828a [file] [log] [blame]
developera6304632020-09-08 14:36:07 +0800[diff] [blame]1/*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <lib/mmio.h>
8#include <lib/utils_def.h>
9#include <mtk_dcm_utils.h>
10
11#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
12#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
13 BIT(16) | \
14 BIT(17) | \
15 BIT(18) | \
16 BIT(21))
17#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
18 BIT(16) | \
19 BIT(17) | \
20 BIT(18))
21#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
22#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
23 BIT(16) | \
24 BIT(17) | \
25 BIT(18) | \
26 BIT(21))
27#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
28 BIT(16) | \
29 BIT(17) | \
30 BIT(18))
31#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
32#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
33 (0x0 << 16) | \
34 (0x0 << 17) | \
35 (0x0 << 18) | \
36 (0x0 << 21))
37#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
38 (0x0 << 16) | \
39 (0x0 << 17) | \
40 (0x0 << 18))
41
42bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
43{
44 bool ret = true;
45
46 ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) &
47 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
48 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
49 ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) &
50 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
51 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
52 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
53 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
54 (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
55
56 return ret;
57}
58
59void dcm_mp_cpusys_top_adb_dcm(bool on)
60{
61 if (on) {
62 /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
63 mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
64 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
65 MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
66 mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
67 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
68 MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
69 mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
70 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
71 MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
72 } else {
73 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
74 mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
75 MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
76 MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
77 mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
78 MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
79 MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
80 mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
81 MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
82 MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
83 }
84}
85
86#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
87#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
88#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
89#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
90#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
91#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
92#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
93#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
94#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
95
96bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
97{
98 bool ret = true;
99
100 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
101 MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
102 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
103 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
104 MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
105 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
106 ret &= ((mmio_read_32(MP0_DCM_CFG0) &
107 MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
108 (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
109
110 return ret;
111}
112
113void dcm_mp_cpusys_top_apb_dcm(bool on)
114{
115 if (on) {
116 /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
117 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
118 MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
119 MP_CPUSYS_TOP_APB_DCM_REG0_ON);
120 mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
121 MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
122 MP_CPUSYS_TOP_APB_DCM_REG1_ON);
123 mmio_clrsetbits_32(MP0_DCM_CFG0,
124 MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
125 MP_CPUSYS_TOP_APB_DCM_REG2_ON);
126 } else {
127 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
128 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
129 MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
130 MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
131 mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
132 MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
133 MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
134 mmio_clrsetbits_32(MP0_DCM_CFG0,
135 MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
136 MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
137 }
138}
139
140#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11))
141#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11))
142#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11))
143
144bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
145{
146 bool ret = true;
147
148 ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
149 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
150 (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
151
152 return ret;
153}
154
155void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
156{
157 if (on) {
158 /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
159 mmio_clrsetbits_32(BUS_PLLDIV_CFG,
160 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
161 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
162 } else {
163 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
164 mmio_clrsetbits_32(BUS_PLLDIV_CFG,
165 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
166 MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
167 }
168}
169
170#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
171#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
172#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
173
174bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
175{
176 bool ret = true;
177
178 ret &= ((mmio_read_32(MP0_DCM_CFG7) &
179 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
180 (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
181
182 return ret;
183}
184
185void dcm_mp_cpusys_top_core_stall_dcm(bool on)
186{
187 if (on) {
188 /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
189 mmio_clrsetbits_32(MP0_DCM_CFG7,
190 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
191 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
192 } else {
193 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
194 mmio_clrsetbits_32(MP0_DCM_CFG7,
195 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
196 MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
197 }
198}
199
200#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
201#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
202#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
203
204bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
205{
206 bool ret = true;
207
208 ret &= ((mmio_read_32(MCSI_DCM0) &
209 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
210 (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
211
212 return ret;
213}
214
215void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
216{
217 if (on) {
218 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
219 mmio_clrsetbits_32(MCSI_DCM0,
220 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
221 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
222 } else {
223 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
224 mmio_clrsetbits_32(MCSI_DCM0,
225 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
226 MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
227 }
228}
229
230#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11))
231#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11))
232#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11))
233
234bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
235{
236 bool ret = true;
237
238 ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) &
239 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
240 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
241
242 return ret;
243}
244
245void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
246{
247 if (on) {
248 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
249 mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
250 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
251 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
252 } else {
253 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
254 mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
255 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
256 MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
257 }
258}
259
260#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11))
261#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11))
262#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11))
263
264bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
265{
266 bool ret = true;
267
268 ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) &
269 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
270 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
271
272 return ret;
273}
274
275void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
276{
277 if (on) {
278 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
279 mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
280 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
281 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
282 } else {
283 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
284 mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
285 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
286 MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
287 }
288}
289
290#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11))
291#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11))
292#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11))
293
294bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void)
295{
296 bool ret = true;
297
298 ret &= ((mmio_read_32(CPU_PLLDIV_CFG2) &
299 MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) ==
300 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
301
302 return ret;
303}
304
305void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on)
306{
307 if (on) {
308 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
309 mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
310 MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
311 MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
312 } else {
313 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
314 mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
315 MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
316 MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF);
317 }
318}
319
320#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11))
321#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11))
322#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11))
323
324bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void)
325{
326 bool ret = true;
327
328 ret &= ((mmio_read_32(CPU_PLLDIV_CFG3) &
329 MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) ==
330 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
331
332 return ret;
333}
334
335void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on)
336{
337 if (on) {
338 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
339 mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
340 MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
341 MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
342 } else {
343 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
344 mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
345 MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
346 MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF);
347 }
348}
349
350#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11))
351#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11))
352#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11))
353
354bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void)
355{
356 bool ret = true;
357
358 ret &= ((mmio_read_32(CPU_PLLDIV_CFG4) &
359 MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) ==
360 (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
361
362 return ret;
363}
364
365void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on)
366{
367 if (on) {
368 /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
369 mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
370 MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
371 MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
372 } else {
373 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
374 mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
375 MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
376 MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF);
377 }
378}
379
380#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
381#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
382#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
383
384bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
385{
386 bool ret = true;
387
388 ret &= ((mmio_read_32(MP0_DCM_CFG7) &
389 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
390 (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
391
392 return ret;
393}
394
395void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
396{
397 if (on) {
398 /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
399 mmio_clrsetbits_32(MP0_DCM_CFG7,
400 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
401 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
402 } else {
403 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
404 mmio_clrsetbits_32(MP0_DCM_CFG7,
405 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
406 MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
407 }
408}
409
410#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
411#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
412#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
413
414bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
415{
416 bool ret = true;
417
418 ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
419 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
420 (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
421
422 return ret;
423}
424
425void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
426{
427 if (on) {
428 /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
429 mmio_clrsetbits_32(BUS_PLLDIV_CFG,
430 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
431 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
432 } else {
433 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
434 mmio_clrsetbits_32(BUS_PLLDIV_CFG,
435 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
436 MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
437 }
438}
439
440#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
441 BIT(4))
442#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
443 BIT(4))
444#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
445 (0x0 << 4))
446
447bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
448{
449 bool ret = true;
450
451 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
452 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
453 (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
454
455 return ret;
456}
457
458void dcm_mp_cpusys_top_misc_dcm(bool on)
459{
460 if (on) {
461 /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
462 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
463 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
464 MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
465 } else {
466 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
467 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
468 MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
469 MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
470 }
471}
472
473#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
474#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
475 BIT(1) | \
476 BIT(2) | \
477 BIT(3))
478#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
479#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
480 BIT(1) | \
481 BIT(2) | \
482 BIT(3))
483#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
484#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
485 (0x0 << 1) | \
486 (0x0 << 2) | \
487 (0x0 << 3))
488
489bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
490{
491 bool ret = true;
492
493 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
494 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
495 (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
496 ret &= ((mmio_read_32(MP0_DCM_CFG0) &
497 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
498 (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
499
500 return ret;
501}
502
503void dcm_mp_cpusys_top_mp0_qdcm(bool on)
504{
505 if (on) {
506 /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
507 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
508 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
509 MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
510 mmio_clrsetbits_32(MP0_DCM_CFG0,
511 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
512 MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
513 } else {
514 /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
515 mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
516 MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
517 MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
518 mmio_clrsetbits_32(MP0_DCM_CFG0,
519 MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
520 MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
521 }
522}
523
524#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
525 BIT(1) | \
526 BIT(2) | \
527 BIT(3))
528#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
529 BIT(1) | \
530 BIT(2) | \
531 BIT(3))
532#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
533 (0x0 << 1) | \
534 (0x0 << 2) | \
535 (0x0 << 3))
536
537bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
538{
539 bool ret = true;
540
541 ret &= ((mmio_read_32(EMI_WFIFO) &
542 CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
543 (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
544
545 return ret;
546}
547
548void dcm_cpccfg_reg_emi_wfifo(bool on)
549{
550 if (on) {
551 /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
552 mmio_clrsetbits_32(EMI_WFIFO,
553 CPCCFG_REG_EMI_WFIFO_REG0_MASK,
554 CPCCFG_REG_EMI_WFIFO_REG0_ON);
555 } else {
556 /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
557 mmio_clrsetbits_32(EMI_WFIFO,
558 CPCCFG_REG_EMI_WFIFO_REG0_MASK,
559 CPCCFG_REG_EMI_WFIFO_REG0_OFF);
560 }
561}
562