Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* |
| 3 | * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #include <assert.h> |
| 7 | #include <common/debug.h> |
| 8 | #include <common/runtime_svc.h> |
| 9 | #include <lib/mmio.h> |
| 10 | #include <tools_share/uuid.h> |
| 11 | |
| 12 | #include "socfpga_fcs.h" |
| 13 | #include "socfpga_mailbox.h" |
| 14 | #include "socfpga_reset_manager.h" |
| 15 | #include "socfpga_sip_svc.h" |
| 16 | #include "socfpga_system_manager.h" |
| 17 | |
| 18 | uint32_t intel_ecc_dbe_notification(uint64_t dbe_value) |
| 19 | { |
| 20 | dbe_value &= WARM_RESET_WFI_FLAG; |
| 21 | |
| 22 | /* Trap CPUs in WFI if warm reset flag is set */ |
| 23 | if (dbe_value > 0) { |
| 24 | while (1) { |
| 25 | wfi(); |
| 26 | } |
| 27 | } |
| 28 | |
| 29 | return INTEL_SIP_SMC_STATUS_OK; |
| 30 | } |
| 31 | |
| 32 | bool cold_reset_for_ecc_dbe(void) |
| 33 | { |
| 34 | uint32_t dbe_int_status; |
| 35 | |
| 36 | dbe_int_status = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)); |
| 37 | |
| 38 | /* Trigger cold reset only for error in critical memory (DDR/OCRAM) */ |
| 39 | dbe_int_status &= SYSMGR_ECC_DBE_COLD_RST_MASK; |
| 40 | |
| 41 | if (dbe_int_status > 0) { |
| 42 | return true; |
| 43 | } |
| 44 | |
| 45 | return false; |
| 46 | } |