| developer | ddb7f40 | 2021-04-08 16:37:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PMIC_WRAP_INIT_H |
| 8 | #define PMIC_WRAP_INIT_H |
| 9 | |
| 10 | #include <stdint.h> |
| 11 | |
| 12 | #include "platform_def.h" |
| 13 | |
| 14 | /* external API */ |
| 15 | int32_t pwrap_read(uint32_t adr, uint32_t *rdata); |
| 16 | int32_t pwrap_write(uint32_t adr, uint32_t wdata); |
| 17 | |
| 18 | static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE; |
| 19 | |
| 20 | /* PMIC_WRAP registers */ |
| 21 | struct mt8195_pmic_wrap_regs { |
| 22 | uint32_t init_done; |
| 23 | uint32_t reserved[543]; |
| 24 | uint32_t wacs2_cmd; |
| 25 | uint32_t wacs2_wdata; |
| 26 | uint32_t reserved1[3]; |
| 27 | uint32_t wacs2_rdata; |
| 28 | uint32_t reserved2[3]; |
| 29 | uint32_t wacs2_vldclr; |
| 30 | uint32_t wacs2_sta; |
| 31 | }; |
| 32 | |
| 33 | #define GET_WACS_FSM(x) ((x >> 1) & 0x7) |
| 34 | |
| 35 | /* macro for SWINF_FSM */ |
| 36 | #define SWINF_FSM_IDLE (0x00) |
| 37 | #define SWINF_FSM_REQ (0x02) |
| 38 | #define SWINF_FSM_WFDLE (0x04) |
| 39 | #define SWINF_FSM_WFVLDCLR (0x06) |
| 40 | #define SWINF_INIT_DONE (0x01) |
| 41 | |
| 42 | /* timeout setting */ |
| 43 | #define PWRAP_READ_US 1000 |
| 44 | #define PWRAP_WAIT_IDLE_US 1000 |
| 45 | |
| 46 | /* error information flag */ |
| 47 | enum pwrap_errno { |
| 48 | E_PWR_INVALID_ARG = 1, |
| 49 | E_PWR_INVALID_RW = 2, |
| 50 | E_PWR_INVALID_ADDR = 3, |
| 51 | E_PWR_INVALID_WDAT = 4, |
| 52 | E_PWR_INVALID_OP_MANUAL = 5, |
| 53 | E_PWR_NOT_IDLE_STATE = 6, |
| 54 | E_PWR_NOT_INIT_DONE = 7, |
| 55 | E_PWR_NOT_INIT_DONE_READ = 8, |
| 56 | E_PWR_WAIT_IDLE_TIMEOUT = 9, |
| 57 | E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, |
| 58 | E_PWR_INIT_SIDLY_FAIL = 11, |
| 59 | E_PWR_RESET_TIMEOUT = 12, |
| 60 | E_PWR_TIMEOUT = 13, |
| 61 | E_PWR_INIT_RESET_SPI = 20, |
| 62 | E_PWR_INIT_SIDLY = 21, |
| 63 | E_PWR_INIT_REG_CLOCK = 22, |
| 64 | E_PWR_INIT_ENABLE_PMIC = 23, |
| 65 | E_PWR_INIT_DIO = 24, |
| 66 | E_PWR_INIT_CIPHER = 25, |
| 67 | E_PWR_INIT_WRITE_TEST = 26, |
| 68 | E_PWR_INIT_ENABLE_CRC = 27, |
| 69 | E_PWR_INIT_ENABLE_DEWRAP = 28, |
| 70 | E_PWR_INIT_ENABLE_EVENT = 29, |
| 71 | E_PWR_READ_TEST_FAIL = 30, |
| 72 | E_PWR_WRITE_TEST_FAIL = 31, |
| 73 | E_PWR_SWITCH_DIO = 32 |
| 74 | }; |
| 75 | |
| 76 | #endif /* PMIC_WRAP_INIT_H */ |