Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLATFORM_DEF_H__ |
| 32 | #define __PLATFORM_DEF_H__ |
| 33 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 34 | #include <arm_def.h> |
| 35 | #include <board_arm_def.h> |
| 36 | #include <common_def.h> |
| 37 | #include <tzc400.h> |
| 38 | #include <v2m_def.h> |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 39 | #include "../fvp_def.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 40 | |
| 41 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 42 | /* |
| 43 | * Most platform porting definitions provided by included headers |
| 44 | */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 45 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 46 | /* |
| 47 | * Required ARM standard platform porting definitions |
| 48 | */ |
| 49 | #define PLAT_ARM_CLUSTER0_CORE_COUNT 4 |
| 50 | #define PLAT_ARM_CLUSTER1_CORE_COUNT 4 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 51 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 52 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 |
| 53 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 54 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 55 | #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 |
| 56 | #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 57 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 58 | /* No SCP in FVP */ |
| 59 | #define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0) |
Juan Castillo | 9246ab8 | 2015-01-28 16:46:57 +0000 | [diff] [blame] | 60 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 61 | #define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) |
Juan Castillo | d227d8b | 2015-01-07 13:49:59 +0000 | [diff] [blame] | 62 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 63 | #define PLAT_ARM_SHARED_RAM_CACHED 1 |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 64 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 65 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 66 | * Load address of BL3-3 for this platform port |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 67 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 68 | #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 69 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 70 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 71 | /* |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 72 | * PL011 related constants |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 73 | */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 74 | #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE |
| 75 | #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 76 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 77 | #define PLAT_ARM_CRASH_UART_BASE V2M_IOFPGA_UART1_BASE |
| 78 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 79 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 80 | #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE |
| 81 | #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ |
Dan Handley | 4fd2f5c | 2014-08-04 11:41:20 +0100 | [diff] [blame] | 82 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 83 | /* CCI related constants */ |
| 84 | #define PLAT_ARM_CCI_BASE 0x2c090000 |
| 85 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 86 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 |
Juan Castillo | e33ee5f | 2014-12-19 09:51:00 +0000 | [diff] [blame] | 87 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 88 | /* TrustZone controller related constants |
| 89 | * |
| 90 | * Currently only filters 0 and 2 are connected on Base FVP. |
| 91 | * Filter 0 : CPU clusters (no access to DRAM by default) |
| 92 | * Filter 1 : not connected |
| 93 | * Filter 2 : LCDs (access to VRAM allowed by default) |
| 94 | * Filter 3 : not connected |
| 95 | * Programming unconnected filters will have no effect at the |
| 96 | * moment. These filter could, however, be connected in future. |
| 97 | * So care should be taken not to configure the unused filters. |
| 98 | * |
| 99 | * Allow only non-secure access to all DRAM to supported devices. |
| 100 | * Give access to the CPUs and Virtio. Some devices |
| 101 | * would normally use the default ID so allow that too. |
| 102 | */ |
| 103 | #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 104 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 105 | #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ |
| 106 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ |
| 107 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ |
| 108 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ |
| 109 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ |
| 110 | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 111 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 112 | |
| 113 | #endif /* __PLATFORM_DEF_H__ */ |