Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | #include <assert.h> |
| 33 | #include <debug.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 34 | #include <memctrl.h> |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 35 | #include <memctrl_v1.h> |
| 36 | #include <mmio.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 37 | #include <string.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 38 | #include <tegra_def.h> |
Douglas Raillard | a8954fc | 2017-01-26 15:54:44 +0000 | [diff] [blame] | 39 | #include <utils.h> |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 40 | #include <xlat_tables_v2.h> |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 41 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 42 | #define TEGRA_GPU_RESET_REG_OFFSET 0x28c |
| 43 | #define GPU_RESET_BIT (1 << 24) |
| 44 | |
| 45 | /* Video Memory base and size (live values) */ |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 46 | static uint64_t video_mem_base; |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 47 | static uint64_t video_mem_size; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Init SMMU. |
| 51 | */ |
| 52 | void tegra_memctrl_setup(void) |
| 53 | { |
| 54 | /* |
| 55 | * Setup the Memory controller to allow only secure accesses to |
| 56 | * the TZDRAM carveout |
| 57 | */ |
Varun Wadekar | 7a9a285 | 2015-09-18 11:21:22 +0530 | [diff] [blame] | 58 | INFO("Tegra Memory Controller (v1)\n"); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 59 | |
| 60 | /* allow translations for all MC engines */ |
| 61 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, |
| 62 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 63 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, |
| 64 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 65 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, |
| 66 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 67 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, |
| 68 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 69 | tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, |
| 70 | (unsigned int)MC_SMMU_TRANSLATION_ENABLE); |
| 71 | |
| 72 | tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); |
| 73 | |
| 74 | tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); |
| 75 | tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); |
| 76 | |
| 77 | /* flush PTC and TLB */ |
| 78 | tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); |
| 79 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
| 80 | tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); |
| 81 | |
| 82 | /* enable SMMU */ |
| 83 | tegra_mc_write_32(MC_SMMU_CONFIG_0, |
| 84 | MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); |
| 85 | (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 86 | |
| 87 | /* video memory carveout */ |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 88 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 89 | (uint32_t)(video_mem_base >> 32)); |
| 90 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)video_mem_base); |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 91 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 95 | * Restore Memory Controller settings after "System Suspend" |
| 96 | */ |
| 97 | void tegra_memctrl_restore_settings(void) |
| 98 | { |
| 99 | tegra_memctrl_setup(); |
| 100 | } |
| 101 | |
| 102 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 103 | * Secure the BL31 DRAM aperture. |
| 104 | * |
| 105 | * phys_base = physical base of TZDRAM aperture |
| 106 | * size_in_bytes = size of aperture in bytes |
| 107 | */ |
| 108 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 109 | { |
| 110 | /* |
| 111 | * Setup the Memory controller to allow only secure accesses to |
| 112 | * the TZDRAM carveout |
| 113 | */ |
| 114 | INFO("Configuring TrustZone DRAM Memory Carveout\n"); |
| 115 | |
| 116 | tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); |
| 117 | tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); |
| 118 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 119 | |
Varun Wadekar | 0dc9181 | 2015-12-30 15:06:41 -0800 | [diff] [blame] | 120 | /* |
| 121 | * Secure the BL31 TZRAM aperture. |
| 122 | * |
| 123 | * phys_base = physical base of TZRAM aperture |
| 124 | * size_in_bytes = size of aperture in bytes |
| 125 | */ |
| 126 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 127 | { |
| 128 | /* |
| 129 | * The v1 hardware controller does not have any registers |
| 130 | * for setting up the on-chip TZRAM. |
| 131 | */ |
| 132 | } |
| 133 | |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 134 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 135 | unsigned long long non_overlap_area_size) |
| 136 | { |
| 137 | /* |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 138 | * Map the NS memory first, clean it and then unmap it. |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 139 | */ |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 140 | mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
| 141 | non_overlap_area_start, /* VA */ |
| 142 | non_overlap_area_size, /* size */ |
| 143 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
| 144 | |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 145 | zeromem((void *)non_overlap_area_start, non_overlap_area_size); |
Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 146 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 147 | |
| 148 | mmap_remove_dynamic_region(non_overlap_area_start, |
| 149 | non_overlap_area_size); |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 150 | } |
| 151 | |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 152 | /* |
| 153 | * Program the Video Memory carveout region |
| 154 | * |
| 155 | * phys_base = physical base of aperture |
| 156 | * size_in_bytes = size of aperture in bytes |
| 157 | */ |
| 158 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 159 | { |
| 160 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); |
| 161 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
| 162 | uint32_t regval; |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 163 | unsigned long long non_overlap_area_size; |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 164 | |
| 165 | /* |
| 166 | * The GPU is the user of the Video Memory region. In order to |
| 167 | * transition to the new memory region smoothly, we program the |
| 168 | * new base/size ONLY if the GPU is in reset mode. |
| 169 | */ |
| 170 | regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 171 | if ((regval & GPU_RESET_BIT) == 0) { |
| 172 | ERROR("GPU not in reset! Video Memory setup failed\n"); |
| 173 | return; |
| 174 | } |
| 175 | |
| 176 | /* |
| 177 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 178 | * Memory region |
| 179 | */ |
| 180 | INFO("Configuring Video Memory Carveout\n"); |
| 181 | |
| 182 | /* |
| 183 | * Configure Memory Controller directly for the first time. |
| 184 | */ |
| 185 | if (video_mem_base == 0) |
| 186 | goto done; |
| 187 | |
| 188 | /* |
| 189 | * Clear the old regions now being exposed. The following cases |
| 190 | * can occur - |
| 191 | * |
| 192 | * 1. clear whole old region (no overlap with new region) |
| 193 | * 2. clear old sub-region below new base |
| 194 | * 3. clear old sub-region above new end |
| 195 | */ |
| 196 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 197 | |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 198 | if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 199 | tegra_clear_videomem(video_mem_base, video_mem_size << 20); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 200 | } else { |
| 201 | if (video_mem_base < phys_base) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 202 | non_overlap_area_size = phys_base - video_mem_base; |
| 203 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 204 | } |
| 205 | if (vmem_end_old > vmem_end_new) { |
Vikram Kanigiri | 4489ad1 | 2015-09-10 14:12:36 +0100 | [diff] [blame] | 206 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
| 207 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
Varun Wadekar | 1be2f97 | 2015-08-26 15:06:14 +0530 | [diff] [blame] | 208 | } |
| 209 | } |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 210 | |
| 211 | done: |
Varun Wadekar | 64443ca | 2016-12-12 16:14:57 -0800 | [diff] [blame] | 212 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32)); |
| 213 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
Varun Wadekar | 7a269e2 | 2015-06-10 14:04:32 +0530 | [diff] [blame] | 214 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
| 215 | |
| 216 | /* store new values */ |
| 217 | video_mem_base = phys_base; |
| 218 | video_mem_size = size_in_bytes >> 20; |
| 219 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 220 | |
| 221 | /* |
| 222 | * During boot, USB3 and flash media (SDMMC/SATA) devices need access to |
| 223 | * IRAM. Because these clients connect to the MC and do not have a direct |
| 224 | * path to the IRAM, the MC implements AHB redirection during boot to allow |
| 225 | * path to IRAM. In this mode, accesses to a programmed memory address aperture |
| 226 | * are directed to the AHB bus, allowing access to the IRAM. The AHB aperture |
| 227 | * is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are |
| 228 | * initialized to disable this aperture. |
| 229 | * |
| 230 | * Once bootup is complete, we must program IRAM base to 0xffffffff and |
| 231 | * IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then |
| 232 | * potentially accessible in this address range. These aperture registers |
| 233 | * also have an access_control/lock bit. After disabling the aperture, the |
| 234 | * access_control register should be programmed to lock the registers. |
| 235 | */ |
| 236 | void tegra_memctrl_disable_ahb_redirection(void) |
| 237 | { |
| 238 | /* program the aperture registers */ |
| 239 | tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF); |
| 240 | tegra_mc_write_32(MC_IRAM_TOP_LO, 0); |
| 241 | tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0); |
| 242 | |
| 243 | /* lock the aperture registers */ |
| 244 | tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES); |
| 245 | } |