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git01.mediatek.com / filogic / atf / d9ce7b1f4cde47fb5f5e4d20ed1920bc70e0e622 / . / plat / amlogic / axg / axg_bl31_setup.c
blob: 9240462e01524dd3bbe796d4614b505c7c4b739a [file] [log] [blame]
Carlo Caioned9ce7b12020-01-24 16:20:15 +0100[diff] [blame^]1/*
2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <common/bl_common.h>
9#include <common/interrupt_props.h>
10#include <drivers/arm/gicv2.h>
11#include <lib/mmio.h>
12#include <lib/xlat_tables/xlat_mmu_helpers.h>
13#include <plat/common/platform.h>
14#include <platform_def.h>
15
16#include "aml_private.h"
17
18/*
19 * Placeholder variables for copying the arguments that have been passed to
20 * BL31 from BL2.
21 */
22static entry_point_info_t bl32_image_ep_info;
23static entry_point_info_t bl33_image_ep_info;
24static image_info_t bl30_image_info;
25static image_info_t bl301_image_info;
26
27/*******************************************************************************
28 * Return a pointer to the 'entry_point_info' structure of the next image for
29 * the security state specified. BL33 corresponds to the non-secure image type
30 * while BL32 corresponds to the secure image type. A NULL pointer is returned
31 * if the image does not exist.
32 ******************************************************************************/
33entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
34{
35 entry_point_info_t *next_image_info;
36
37 next_image_info = (type == NON_SECURE) ?
38 &bl33_image_ep_info : &bl32_image_ep_info;
39
40 /* None of the images can have 0x0 as the entrypoint. */
41 if (next_image_info->pc != 0U)
42 return next_image_info;
43
44 return NULL;
45}
46
47/*******************************************************************************
48 * Perform any BL31 early platform setup. Here is an opportunity to copy
49 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
50 * they are lost (potentially). This needs to be done before the MMU is
51 * initialized so that the memory layout can be used while creating page
52 * tables. BL2 has flushed this information to memory, so we are guaranteed
53 * to pick up good data.
54 ******************************************************************************/
55struct axg_bl31_param {
56 param_header_t h;
57 image_info_t *bl31_image_info;
58 entry_point_info_t *bl32_ep_info;
59 image_info_t *bl32_image_info;
60 entry_point_info_t *bl33_ep_info;
61 image_info_t *bl33_image_info;
62 image_info_t *scp_image_info[];
63};
64
65void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
66 u_register_t arg2, u_register_t arg3)
67{
68 struct axg_bl31_param *from_bl2;
69
70 /* Initialize the console to provide early debug support */
71 aml_console_init();
72
73 from_bl2 = (struct axg_bl31_param *)arg0;
74
75 /* Check params passed from BL2 are not NULL. */
76 assert(from_bl2 != NULL);
77 assert(from_bl2->h.type == PARAM_BL31);
78 assert(from_bl2->h.version >= VERSION_1);
79
80 /*
81 * Copy BL32 and BL33 entry point information. It is stored in Secure
82 * RAM, in BL2's address space.
83 */
84 bl32_image_ep_info = *from_bl2->bl32_ep_info;
85 bl33_image_ep_info = *from_bl2->bl33_ep_info;
86
87 if (bl33_image_ep_info.pc == 0U) {
88 ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
89 panic();
90 }
91
92 bl30_image_info = *from_bl2->scp_image_info[0];
93 bl301_image_info = *from_bl2->scp_image_info[1];
94}
95
96void bl31_plat_arch_setup(void)
97{
98 aml_setup_page_tables();
99
100 enable_mmu_el3(0);
101}
102
103static inline bool axg_scp_ready(void)
104{
105 return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
106}
107
108static inline void axg_scp_boot(void)
109{
110 aml_scpi_upload_scp_fw(bl30_image_info.image_base,
111 bl30_image_info.image_size, 0);
112 aml_scpi_upload_scp_fw(bl301_image_info.image_base,
113 bl301_image_info.image_size, 1);
114 while (!axg_scp_ready())
115 ;
116}
117
118/*******************************************************************************
119 * GICv2 driver setup information
120 ******************************************************************************/
121static const interrupt_prop_t axg_interrupt_props[] = {
122 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
123 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
124 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
125 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
126 INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
127 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
128 INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
129 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
130 INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
131 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
132 INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
133 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
134 INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
135 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
136 INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
137 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
138 INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
139 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
140};
141
142static const gicv2_driver_data_t axg_gic_data = {
143 .gicd_base = AML_GICD_BASE,
144 .gicc_base = AML_GICC_BASE,
145 .interrupt_props = axg_interrupt_props,
146 .interrupt_props_num = ARRAY_SIZE(axg_interrupt_props)
147};
148
149void bl31_platform_setup(void)
150{
151 aml_mhu_secure_init();
152
153 gicv2_driver_init(&axg_gic_data);
154 gicv2_distif_init();
155 gicv2_pcpu_distif_init();
156 gicv2_cpuif_enable();
157
158 axg_scp_boot();
159}