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Jiafei Panb4ccced2022-01-20 17:40:16 +08001/*
2 * Copyright 2018-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <arch.h>
10#include <caam.h>
11#include <cassert.h>
12#include <cci.h>
13#include <common/debug.h>
14#include <dcfg.h>
15#ifdef I2C_INIT
16#include <i2c.h>
17#endif
18#include <lib/mmio.h>
19#include <lib/xlat_tables/xlat_tables_v2.h>
20#include <ls_interconnect.h>
21#ifdef POLICY_FUSE_PROVISION
22#include <nxp_gpio.h>
23#endif
Jiafei Panb4ccced2022-01-20 17:40:16 +080024#include <nxp_smmu.h>
Jiafei Panb4ccced2022-01-20 17:40:16 +080025#include <nxp_timer.h>
26#include <plat_console.h>
27#include <plat_gic.h>
28#include <plat_tzc400.h>
29#include <scfg.h>
30#if defined(NXP_SFP_ENABLED)
31#include <sfp.h>
32#endif
33
34#include <errata.h>
35#include <ns_access.h>
36#ifdef CONFIG_OCRAM_ECC_EN
37#include <ocram.h>
38#endif
39#include <plat_common.h>
40#include <platform_def.h>
41#include <soc.h>
42
43static dcfg_init_info_t dcfg_init_data = {
44 .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
45 .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
46 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
47 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
48};
49
50/* Function to return the SoC SYS CLK */
51static unsigned int get_sys_clk(void)
52{
53 return NXP_SYSCLK_FREQ;
54}
55
56/*
57 * Function returns the base counter frequency
58 * after reading the first entry at CNTFID0 (0x20 offset).
59 *
60 * Function is used by:
61 * 1. ARM common code for PSCI management.
62 * 2. ARM Generic Timer init.
63 *
64 */
65unsigned int plat_get_syscnt_freq2(void)
66{
67 unsigned int counter_base_frequency;
68
69 counter_base_frequency = get_sys_clk() / 4;
70
71 return counter_base_frequency;
72}
73
74#ifdef IMAGE_BL2
75/* Functions for BL2 */
76
77static struct soc_type soc_list[] = {
78 SOC_ENTRY(LS1046A, LS1046A, 1, 4),
79 SOC_ENTRY(LS1046AE, LS1046AE, 1, 4),
80 SOC_ENTRY(LS1026A, LS1026A, 1, 2),
81 SOC_ENTRY(LS1026AE, LS1026AE, 1, 2),
82};
83
84#ifdef POLICY_FUSE_PROVISION
85static gpio_init_info_t gpio_init_data = {
86 .gpio1_base_addr = NXP_GPIO1_ADDR,
87 .gpio2_base_addr = NXP_GPIO2_ADDR,
88 .gpio3_base_addr = NXP_GPIO3_ADDR,
89 .gpio4_base_addr = NXP_GPIO4_ADDR,
90};
91#endif
92
93/*
94 * Function to set the base counter frequency at
95 * the first entry of the Frequency Mode Table,
96 * at CNTFID0 (0x20 offset).
97 *
98 * Set the value of the pirmary core register cntfrq_el0.
99 */
100static void set_base_freq_CNTFID0(void)
101{
102 /*
103 * Below register specifies the base frequency of the system counter.
104 * As per NXP Board Manuals:
105 * The system counter always works with SYS_REF_CLK/4 frequency clock.
106 */
107 unsigned int counter_base_frequency = get_sys_clk() / 4;
108
109 /* Setting the frequency in the Frequency modes table.
110 *
111 * Note: The value for ls1046ardb board at this offset
112 * is not RW as stated. This offset have the
113 * fixed value of 100000400 Hz.
114 *
115 * The below code line has no effect.
116 * Keeping it for other platforms where it has effect.
117 */
118 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
119
120 write_cntfrq_el0(counter_base_frequency);
121}
122
123void soc_preload_setup(void)
124{
125
126}
127
128/*
129 * This function implements soc specific erratas
130 * This is called before DDR is initialized or MMU is enabled
131 */
132void soc_early_init(void)
133{
134 uint8_t num_clusters, cores_per_cluster;
135 dram_regions_info_t *dram_regions_info = get_dram_regions_info();
136
137#ifdef CONFIG_OCRAM_ECC_EN
138 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
139#endif
140 dcfg_init(&dcfg_init_data);
141#ifdef POLICY_FUSE_PROVISION
142 gpio_init(&gpio_init_data);
143 sec_init(NXP_CAAM_ADDR);
144#endif
145#if LOG_LEVEL > 0
146 /* Initialize the console to provide early debug support */
147
148 plat_console_init(NXP_CONSOLE_ADDR,
149 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
150#endif
151 set_base_freq_CNTFID0();
152
153 /* Enable snooping on SEC read and write transactions */
154 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
155 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
156
157 /*
158 * Initialize Interconnect for this cluster during cold boot.
159 * No need for locks as no other CPU is active.
160 */
161 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
162
163 /*
164 * Enable Interconnect coherency for the primary CPU's cluster.
165 */
166 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
167 plat_ls_interconnect_enter_coherency(num_clusters);
168
Howard Lub41f1ed2022-11-01 19:45:46 +0800169 /*
170 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
171 */
172 smmu_cache_unlock(NXP_SMMU_ADDR);
173 INFO("SMMU Cache Unlocking is Configured.\n");
174
Jiafei Panb4ccced2022-01-20 17:40:16 +0800175#if TRUSTED_BOARD_BOOT
176 uint32_t mode;
177
178 sfp_init(NXP_SFP_ADDR);
179 /*
180 * For secure boot disable SMMU.
181 * Later when platform security policy comes in picture,
182 * this might get modified based on the policy
183 */
184 if (check_boot_mode_secure(&mode) == true) {
185 bypass_smmu(NXP_SMMU_ADDR);
186 }
187
188 /*
189 * For Mbedtls currently crypto is not supported via CAAM
190 * enable it when that support is there. In tbbr.mk
191 * the CAAM_INTEG is set as 0.
192 */
193#ifndef MBEDTLS_X509
194 /* Initialize the crypto accelerator if enabled */
195 if (is_sec_enabled() == false) {
196 INFO("SEC is disabled.\n");
197 } else {
198 sec_init(NXP_CAAM_ADDR);
199 }
200#endif
201#elif defined(POLICY_FUSE_PROVISION)
202 gpio_init(&gpio_init_data);
203 sfp_init(NXP_SFP_ADDR);
204 sec_init(NXP_CAAM_ADDR);
205#endif
206
207 soc_errata();
208
209 /* Initialize system level generic timer for Layerscape Socs. */
210 delay_timer_init(NXP_TIMER_ADDR);
211
212#ifdef DDR_INIT
213 i2c_init(NXP_I2C_ADDR);
214 dram_regions_info->total_dram_size = init_ddr();
215#endif
216}
217
218void soc_bl2_prepare_exit(void)
219{
220#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
221 set_sfp_wr_disable();
222#endif
223}
224
225/* This function returns the boot device based on RCW_SRC */
226enum boot_device get_boot_dev(void)
227{
228 enum boot_device src = BOOT_DEVICE_NONE;
229 uint32_t porsr1;
230 uint32_t rcw_src, val;
231
232 porsr1 = read_reg_porsr1();
233
234 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
235
236 val = rcw_src & RCW_SRC_NAND_MASK;
237
238 if (val == RCW_SRC_NAND_VAL) {
239 val = rcw_src & NAND_RESERVED_MASK;
240 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
241 src = BOOT_DEVICE_IFC_NAND;
242 INFO("RCW BOOT SRC is IFC NAND\n");
243 }
244 } else {
245 /* RCW SRC NOR */
246 val = rcw_src & RCW_SRC_NOR_MASK;
247 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
248 src = BOOT_DEVICE_IFC_NOR;
249 INFO("RCW BOOT SRC is IFC NOR\n");
250 } else {
251 switch (rcw_src) {
252 case QSPI_VAL1:
253 case QSPI_VAL2:
254 src = BOOT_DEVICE_QSPI;
255 INFO("RCW BOOT SRC is QSPI\n");
256 break;
257 case SD_VAL:
258 src = BOOT_DEVICE_EMMC;
259 INFO("RCW BOOT SRC is SD/EMMC\n");
260 break;
261 default:
262 src = BOOT_DEVICE_NONE;
263 }
264 }
265 }
266
267 return src;
268}
269
270/* This function sets up access permissions on memory regions */
271void soc_mem_access(void)
272{
273 dram_regions_info_t *info_dram_regions = get_dram_regions_info();
274 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
275 unsigned int dram_idx, index = 0U;
276
277 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
278 dram_idx++) {
279 if (info_dram_regions->region[dram_idx].size == 0) {
280 ERROR("DDR init failure, or");
281 ERROR("DRAM regions not populated correctly.\n");
282 break;
283 }
284
285 index = populate_tzc400_reg_list(tzc400_reg_list,
286 dram_idx, index,
287 info_dram_regions->region[dram_idx].addr,
288 info_dram_regions->region[dram_idx].size,
289 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
290 }
291
292 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list);
293}
294
295#else /* IMAGE_BL2 */
296/* Functions for BL31 */
297
298const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
299
300CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
301 assert_invalid_ls1046_cluster_count);
302
303/* This function returns the SoC topology */
304const unsigned char *plat_get_power_domain_tree_desc(void)
305{
306 return _power_domain_tree_desc;
307}
308
309/*
310 * This function returns the core count within the cluster corresponding to
311 * `mpidr`.
312 */
313unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
314{
315 return CORES_PER_CLUSTER;
316}
317
318void soc_early_platform_setup2(void)
319{
320 dcfg_init(&dcfg_init_data);
321 /* Initialize system level generic timer for SoCs */
322 delay_timer_init(NXP_TIMER_ADDR);
323
324#if LOG_LEVEL > 0
325 /* Initialize the console to provide early debug support */
326 plat_console_init(NXP_CONSOLE_ADDR,
327 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
328#endif
329}
330
331void soc_platform_setup(void)
332{
333 static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
334 /*
335 * On a GICv2 system, the Group 1 secure interrupts are treated
336 * as Group 0 interrupts.
337 */
338 static interrupt_prop_t ls_interrupt_props[] = {
339 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
340 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
341 };
342
343 plat_ls_gic_driver_init(
344#if (TEST_BL31)
345 /* Defect in simulator - GIC base addresses (4Kb aligned) */
346 NXP_GICD_4K_ADDR,
347 NXP_GICC_4K_ADDR,
348#else
349 NXP_GICD_64K_ADDR,
350 NXP_GICC_64K_ADDR,
351#endif
352 PLATFORM_CORE_COUNT,
353 ls_interrupt_props,
354 ARRAY_SIZE(ls_interrupt_props),
355 target_mask_array);
356
357 plat_ls_gic_init();
358 enable_init_timer();
359}
360
361/* This function initializes the soc from the BL31 module */
362void soc_init(void)
363{
364 /* low-level init of the soc */
365 soc_init_lowlevel();
366 _init_global_data();
367 soc_init_percpu();
368 _initialize_psci();
369
370 /*
371 * Initialize the interconnect during cold boot.
372 * No need for locks as no other CPU is active.
373 */
374 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
375
376 /*
377 * Enable coherency in interconnect for the primary CPU's cluster.
378 * Earlier bootloader stages might already do this but we can't
379 * assume so. No harm in executing this code twice.
380 */
381 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
382
383 /* Init CSU to enable non-secure access to peripherals */
384 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
385
386 /* Initialize the crypto accelerator if enabled */
387 if (is_sec_enabled() == false) {
388 INFO("SEC is disabled.\n");
389 } else {
390 sec_init(NXP_CAAM_ADDR);
391 }
392}
393
394void soc_runtime_setup(void)
395{
396
397}
398
399#endif /* IMAGE_BL2 */