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git01.mediatek.com / filogic / atf / d973c03545e20cdddef25d0041936080f3f3a60e / . / plat / marvell / a8k / common / include / platform_def.h
blob: ed7bb63da9f788e509ce4bb3599067d6fd6a2bd4 [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8#ifndef __PLATFORM_DEF_H__
9#define __PLATFORM_DEF_H__
10
11#include <board_marvell_def.h>
12#include <gic_common.h>
13#include <interrupt_props.h>
14#include <mvebu_def.h>
15#ifndef __ASSEMBLY__
16#include <stdio.h>
17#endif /* __ASSEMBLY__ */
18
19/*
20 * Most platform porting definitions provided by included headers
21 */
22
23/*
24 * DRAM Memory layout:
25 * +-----------------------+
26 * : :
27 * : Linux :
28 * 0x04X00000-->+-----------------------+
29 * | BL3-3(u-boot) |>>}>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
30 * |-----------------------| } |
31 * | BL3-[0,1, 2] | }---------------------------------> |
32 * |-----------------------| } || |
33 * | BL2 | }->FIP (loaded by || |
34 * |-----------------------| } BootROM to DRAM) || |
35 * | FIP_TOC | } || |
36 * 0x04120000-->|-----------------------| || |
37 * | BL1 (RO) | || |
38 * 0x04100000-->+-----------------------+ || |
39 * : : || |
40 * : Trusted SRAM section : \/ |
41 * 0x04040000-->+-----------------------+ Replaced by BL2 +----------------+ |
42 * | BL1 (RW) | <<<<<<<<<<<<<<<< | BL3-1 NOBITS | |
43 * 0x04037000-->|-----------------------| <<<<<<<<<<<<<<<< |----------------| |
44 * | | <<<<<<<<<<<<<<<< | BL3-1 PROGBITS | |
45 * 0x04023000-->|-----------------------| +----------------+ |
46 * | BL2 | |
47 * |-----------------------| |
48 * | | |
49 * 0x04001000-->|-----------------------| |
50 * | Shared | |
51 * 0x04000000-->+-----------------------+ |
52 * : : |
53 * : Linux : |
54 * : : |
55 * |-----------------------| |
56 * | | U-Boot(BL3-3) Loaded by BL2 |
57 * | U-Boot | <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
58 * 0x00000000-->+-----------------------+
59 *
60 * Trusted SRAM section 0x4000000..0x4200000:
61 * ----------------------------------------
62 * SRAM_BASE = 0x4001000
63 * BL2_BASE = 0x4006000
64 * BL2_LIMIT = BL31_BASE
65 * BL31_BASE = 0x4023000 = (64MB + 256KB - 0x1D000)
66 * BL31_PROGBITS_LIMIT = BL1_RW_BASE
67 * BL1_RW_BASE = 0x4037000 = (64MB + 256KB - 0x9000)
68 * BL1_RW_LIMIT = BL31_LIMIT = 0x4040000
69 *
70 *
71 * PLAT_MARVELL_FIP_BASE = 0x4120000
72 */
73
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]74#define PLAT_MARVELL_SRAM_BASE 0xFFE1C048
75#define PLAT_MARVELL_SRAM_END 0xFFE78000
76
77#define PLAT_MARVELL_ATF_BASE 0x4000000
78#define PLAT_MARVELL_ATF_LOAD_ADDR (PLAT_MARVELL_ATF_BASE + \
79 0x100000)
80
81#define PLAT_MARVELL_FIP_BASE (PLAT_MARVELL_ATF_LOAD_ADDR + \
82 0x20000)
83#define PLAT_MARVELL_FIP_MAX_SIZE 0x4000000
84
85#define PLAT_MARVELL_NORTHB_COUNT 1
86
87#define PLAT_MARVELL_CLUSTER_COUNT 2
88#define PLAT_MARVELL_CLUSTER_CORE_COUNT 2
89
90#define PLAT_MARVELL_CORE_COUNT (PLAT_MARVELL_CLUSTER_COUNT * \
91 PLAT_MARVELL_CLUSTER_CORE_COUNT)
92
93/* DRAM[2MB..66MB] is used as Trusted ROM */
94#define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR
95/* 64 MB TODO: reduce this to minimum needed according to fip image size */
96#define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x04000000
97/* Reserve 16M for SCP (Secure PayLoad) Trusted DRAM */
98#define PLAT_MARVELL_TRUSTED_DRAM_BASE 0x04400000
99#define PLAT_MARVELL_TRUSTED_DRAM_SIZE 0x01000000 /* 16 MB */
100
101/*
102 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
103 * plus a little space for growth.
104 */
105#define PLAT_MARVELL_MAX_BL1_RW_SIZE 0xA000
106
107/*
108 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
109 * little space for growth.
110 */
111#define PLAT_MARVELL_MAX_BL2_SIZE 0xF000
112
113/*
114 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
115 * little space for growth.
116 */
117#define PLAT_MARVEL_MAX_BL31_SIZE 0x5D000
118
119#define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE
120
121/* GIC related definitions */
122#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)
123#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)
124
125#define PLAT_MARVELL_G0_IRQ_PROPS(grp) \
126 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
127 GIC_INTR_CFG_LEVEL), \
128 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
Marcin Wojtas0c60c2f2018-03-21 09:59:59 +0100[diff] [blame]129 GIC_INTR_CFG_LEVEL), \
130 INTR_PROP_DESC(MARVELL_IRQ_PIC0, GIC_HIGHEST_SEC_PRIORITY, grp, \
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]131 GIC_INTR_CFG_LEVEL)
132
133#define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \
134 INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
135 grp, GIC_INTR_CFG_LEVEL), \
136 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
137 GIC_INTR_CFG_LEVEL), \
138 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
139 GIC_INTR_CFG_LEVEL), \
140 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
141 GIC_INTR_CFG_LEVEL), \
142 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
143 GIC_INTR_CFG_LEVEL), \
144 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
145 GIC_INTR_CFG_LEVEL), \
146 INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
147 GIC_INTR_CFG_LEVEL)
148
149#define PLAT_MARVELL_SHARED_RAM_CACHED 1
150
151/*
152 * Load address of BL3-3 for this platform port
153 */
154#define PLAT_MARVELL_NS_IMAGE_OFFSET 0x0
155
156/* System Reference Clock*/
157#define PLAT_REF_CLK_IN_HZ COUNTER_FREQUENCY
158
159/*
160 * PL011 related constants
161 */
162#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000)
163#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 200000000
164
165#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
166#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
167
168#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
169#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
170
171/* Recovery image enable */
172#define PLAT_RECOVERY_IMAGE_ENABLE 0
173
174/* Required platform porting definitions */
175#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
176
177/* System timer related constants */
178#define PLAT_MARVELL_NSTIMER_FRAME_ID 1
179
180/* Mailbox base address (note the lower memory space
181 * is reserved for BLE data)
182 */
183#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \
184 + 0x400)
185#define PLAT_MARVELL_MAILBOX_SIZE 0x100
186#define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */
187
188/* Securities */
189#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
190
191#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
192#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
193
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300[diff] [blame^]194#ifdef BL32
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]195#define BL32_BASE TRUSTED_DRAM_BASE
Konstantin Porotchkind973c032018-10-02 17:45:15 +0300[diff] [blame^]196#define BL32_LIMIT TRUSTED_DRAM_SIZE
197#endif
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]198
Marcin Wojtas0c60c2f2018-03-21 09:59:59 +0100[diff] [blame]199#define MVEBU_PMU_IRQ_WA
200
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]201#endif /* __PLATFORM_DEF_H__ */