| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 6 | #ifndef HI3660_HKADC_H |
| 7 | #define HI3660_HKADC_H |
| Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 8 | |
| 9 | #define HKADC_SSI_REG_BASE 0xE82B8000 |
| 10 | |
| 11 | #define HKADC_DSP_START_REG (HKADC_SSI_REG_BASE + 0x000) |
| 12 | #define HKADC_WR_NUM_REG (HKADC_SSI_REG_BASE + 0x008) |
| 13 | #define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C) |
| 14 | #define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020) |
| 15 | |
| 16 | #define WR1_WRITE_MODE (1 << 31) |
| 17 | #define WR1_READ_MODE (0 << 31) |
| 18 | #define WR1_ADDR(x) (((x) & 0x7F) << 24) |
| 19 | #define WR1_DATA(x) (((x) & 0xFF) << 16) |
| 20 | #define WR0_WRITE_MODE (1 << 15) |
| 21 | #define WR0_READ_MODE (0 << 15) |
| 22 | #define WR0_ADDR(x) (((x) & 0x7F) << 8) |
| 23 | #define WR0_DATA(x) ((x) & 0xFF) |
| 24 | |
| 25 | #define HKADC_WR23_DATA_REG (HKADC_SSI_REG_BASE + 0x024) |
| 26 | #define HKADC_WR45_DATA_REG (HKADC_SSI_REG_BASE + 0x028) |
| 27 | #define HKADC_DELAY01_REG (HKADC_SSI_REG_BASE + 0x030) |
| 28 | #define HKADC_DELAY23_REG (HKADC_SSI_REG_BASE + 0x034) |
| 29 | #define HKADC_DELAY45_REG (HKADC_SSI_REG_BASE + 0x038) |
| 30 | #define HKADC_DSP_RD2_DATA_REG (HKADC_SSI_REG_BASE + 0x048) |
| 31 | #define HKADC_DSP_RD3_DATA_REG (HKADC_SSI_REG_BASE + 0x04C) |
| 32 | |
| 33 | /* HKADC Internal Registers */ |
| 34 | #define HKADC_CTRL_ADDR 0x00 |
| 35 | #define HKADC_START_ADDR 0x01 |
| 36 | #define HKADC_DATA1_ADDR 0x03 /* high 8 bits */ |
| 37 | #define HKADC_DATA0_ADDR 0x04 /* low 8 bits */ |
| 38 | #define HKADC_MODE_CFG 0x0A |
| 39 | |
| 40 | #define HKADC_VALUE_HIGH 0x0FF0 |
| 41 | #define HKADC_VALUE_LOW 0x000F |
| 42 | #define HKADC_VALID_VALUE 0x0FFF |
| 43 | |
| 44 | #define HKADC_CHANNEL_MAX 15 |
| 45 | #define HKADC_VREF_1V8 1800 |
| 46 | #define HKADC_ACCURACY 0x0FFF |
| 47 | |
| 48 | #define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \ |
| 49 | (0x1 << 16)) |
| 50 | #define HKADC_WR23_VALUE ((0x1 << 31) | \ |
| 51 | (HKADC_DATA0_ADDR << 24) | \ |
| 52 | (1 << 15) | \ |
| 53 | (HKADC_DATA1_ADDR << 8)) |
| 54 | #define HKADC_WR45_VALUE (0x80) |
| 55 | #define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF) |
| 56 | #define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200) |
| 57 | #define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8) |
| 58 | #define START_DELAY_TIMEOUT 2000 |
| 59 | #define HKADC_WR_NUM_VALUE 4 |
| 60 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 61 | #endif /* HI3660_HKADC_H */ |